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Re: [Qemu-devel] [PATCH v9 00/10] 8bit AVR cores


From: Michael Rolnik
Subject: Re: [Qemu-devel] [PATCH v9 00/10] 8bit AVR cores
Date: Tue, 5 Jul 2016 21:15:44 +0300

Hi Richard,

Are there more pending issues with my code?

Thanks,
Michael

On Sat, Jul 2, 2016 at 10:56 PM, Michael Rolnik <address@hidden> wrote:

> for ADIW, SBIW instructions I modified address calculation.
>
> On Sat, Jul 2, 2016 at 9:20 PM, Michael Rolnik <address@hidden> wrote:
>
>> Hi Richard.
>>
>> I folded all my changes into prevous commits.
>>
>> 1. I meant EOR, which is actually XOR. Prevously it did not save the
>> result into the register
>> 2. my mistake I meant ORI and LDS and not ADIW, SBIW
>> 3. when there is a call to tlb_fill for [0x0000: 0x0100) region it
>>     a. sets env->fullwr
>>     b. calls cpu_loop_exit_restore.
>>     c. the whole block is retranslated and instead of st it generates
>> helper_fullwr for each store within this TB.
>>     d. helper_fullwr calls cpu_physical_memory_write
>>     e. sample_io_write is called and register is changed since the whole
>> thing is done from within a helper
>>     f. this is tested.
>>
>>
>> On Fri, Jul 1, 2016 at 10:09 PM, Richard Henderson <address@hidden>
>> wrote:
>>
>>> On 07/01/2016 07:47 AM, Michael Rolnik wrote:
>>>
>>>> 5. translation bug fixes for ADIW, SBIW, XOR instructions
>>>> 6. propper handling of cpu register writes though memory
>>>>
>>>
>>> I don't see these changes in the patch set.
>>>
>>>
>>> r~
>>>
>>
>>
>>
>> --
>> Best Regards,
>> Michael Rolnik
>>
>
>
>
> --
> Best Regards,
> Michael Rolnik
>



-- 
Best Regards,
Michael Rolnik


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