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[Qemu-devel] [PATCH 4/4] target-mips: enable 10-bit ASIDs in I6400 CPU
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH 4/4] target-mips: enable 10-bit ASIDs in I6400 CPU |
Date: |
Mon, 27 Jun 2016 16:19:12 +0100 |
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c43bdb7..39ed5c4 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -685,7 +685,7 @@ static const mips_def_t mips_defs[] =
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
- (0xfc << CP0C4_KScrExist),
+ (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
(1 << CP0C5_LLB) | (1 << CP0C5_MRP),
.CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
--
2.7.4