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[Qemu-devel] [PULL 08/18] palmetto-bmc: Configure the SCU's hardware str
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/18] palmetto-bmc: Configure the SCU's hardware strapping register |
Date: |
Mon, 27 Jun 2016 15:45:00 +0100 |
From: Andrew Jeffery <address@hidden>
The magic constant configures the following options:
* 28:27: Configure DRAM size as 256MB
* 26:24: DDR3 SDRAM with CL = 6, CWL = 5
* 23: Configure 24/48MHz CLKIN
* 22: Disable GPIOE pass-through mode
* 21: Disable GPIOD pass-through mode
* 20: Enable LPC decode of SuperIO 0x2E/0x4E addresses
* 19: Disable ACPI
* 18: Configure 48MHz CLKIN
* 17: Disable BMC 2nd boot watchdog timer
* 16: Decode SuperIO address 0x2E
* 15: VGA Class Code
* 14: Enable LPC dedicated reset pin
* 13:12: Enable SPI Master and SPI Slave to AHB Bridge
* 11:10: Select CPU:AHB ratio = 2:1
* 9:8: Select 384MHz H-PLL
* 7: Configure MAC#2 for RMII/NCSI
* 6: Configure MAC#1 for RMII/NCSI
* 5: No VGA BIOS ROM
* 4: Boot using 32bit SPI address mode
* 3:2: Select 16MB VGA memory
* 1:0: Boot from SPI flash memory
Signed-off-by: Andrew Jeffery <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/palmetto-bmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c
index a51d960..b8eed21 100644
--- a/hw/arm/palmetto-bmc.c
+++ b/hw/arm/palmetto-bmc.c
@@ -44,6 +44,8 @@ static void palmetto_bmc_init(MachineState *machine)
&bmc->ram);
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
&error_abort);
+ object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",
+ &error_abort);
object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
&error_abort);
--
1.9.1
- [Qemu-devel] [PULL 00/18] target-arm queue, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 16/18] m25p80: Fast read commands family changes., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 14/18] m25p80: Introduce quad and equad modes., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 09/18] m25p80: Replace JEDEC ID masking with function., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 07/18] ast2400: Integrate the SCU model and set silicon revision, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 15/18] m25p80: Introduce configuration registers., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 08/18] palmetto-bmc: Configure the SCU's hardware strapping register,
Peter Maydell <=
- [Qemu-devel] [PULL 05/18] arm: Re-enable tmp105 test, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 18/18] m25p80: Fix WINBOND fast read command handling, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 10/18] m25p80: Make a table for JEDEC ID., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 13/18] m25p80: Add additional flash commands:, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 12/18] m25p80: Introduce COLLECTING_VAR_LEN_DATA state., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 04/18] cadence_gem: Set the last bit when wrap is set, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 01/18] hw/intc/arm_gicv3: Add missing break, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 11/18] m25p80: Allow more than four banks., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 02/18] cadence_uart: Protect against transmit errors, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 17/18] m25p80: New flash devices., Peter Maydell, 2016/06/27