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[Qemu-devel] [RFC v3 PATCH 07/14] tcg/ppc: Add support for fence
From: |
Pranith Kumar |
Subject: |
[Qemu-devel] [RFC v3 PATCH 07/14] tcg/ppc: Add support for fence |
Date: |
Sat, 18 Jun 2016 00:03:36 -0400 |
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Pranith Kumar <address@hidden>
---
tcg/ppc/tcg-target.inc.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index da10052..766848e 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -469,6 +469,10 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define STHX XO31(407)
#define STWX XO31(151)
+#define EIEIO XO31(854)
+#define HWSYNC XO31(598)
+#define LWSYNC (HWSYNC | (1u << 21))
+
#define SPR(a, b) ((((a)<<5)|(b))<<11)
#define LR SPR(8, 0)
#define CTR SPR(9, 0)
@@ -1237,6 +1241,21 @@ static void tcg_out_brcond2 (TCGContext *s, const TCGArg
*args,
tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
}
+static void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ switch (a0 & TCG_MO_ALL) {
+ case TCG_MO_LD_LD:
+ tcg_out32(s, LWSYNC);
+ break;
+ case TCG_MO_ST_ST:
+ tcg_out32(s, EIEIO);
+ break;
+ default:
+ tcg_out32(s, HWSYNC);
+ break;
+ }
+}
+
#ifdef __powerpc64__
void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
{
@@ -2439,6 +2458,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args,
tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, args[0]);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -2586,6 +2609,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
#endif
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.9.0
- [Qemu-devel] [RFC v3 PATCH 07/14] tcg/ppc: Add support for fence,
Pranith Kumar <=