Re: [Qemu-devel] [PATCH v9 09/10] target-mips: Implement FCR31's R/W bitmask and related functionalities

[Leon Alrae]

On Fri, Jun 10, 2016 at 11:57:36AM +0200, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <address@hidden>
> 
> This patch implements read and write access rules for Mips floating
> point control and status register (FCR31). The change can be divided
> into following parts:
> 
> - Add fields that will keep FCR31's R/W bitmask in procesor
>   definitions and processor float_status structure.
> 
> - Add appropriate value for FCR31's R/W bitmask for each supported
>   processor.
> 
> - Add function for setting snan_bit_is_one, and integrate it in
>   appropriate places.
> 
> - Modify handling of CTC1 (case 31) instruction to use FCR31's R/W
>   bitmask.
> 
> - Modify handling user mode executables for Mips, in relation to the
>   bit EF_MIPS_NAN2008 from ELF header, that is in turn related to
>   reading and writing to FCR31.
> 
> - Modify gdb behavior in relation to FCR31.
> 
> Signed-off-by: Thomas Schwinge <address@hidden>
> Signed-off-by: Maciej W. Rozycki <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> ---
>  linux-user/main.c            | 14 ++++++++++++++
>  target-mips/cpu.h            |  8 ++++++++
>  target-mips/gdbstub.c        |  8 +++-----
>  target-mips/op_helper.c      | 14 +++-----------
>  target-mips/translate.c      |  5 ++---
>  target-mips/translate_init.c | 26 ++++++++++++++++++++++++++
>  6 files changed, 56 insertions(+), 19 deletions(-)

Reviewed-by: Leon Alrae <address@hidden>