Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/12] ppc: preparing pnv landing (round 2)

[David Gibson]

On Tue, May 03, 2016 at 06:03:22PM +0200, Cédric Le Goater wrote:
> Hello,
> 
> Here is a new set of fixes extracted from Ben's PowerNV tree :
> 
>      https://github.com/ozbenh/qemu/commits/powernv
> 
> It was quickly tested with a pseries guest using KVM and TCG.

Ok, back now.

I've merged these into ppc-for-2.7 (after today's pull req), except
for 7/12 which I've replied to separately.

> 
> Thanks,
> 
> C.
> 
> Benjamin Herrenschmidt (11):
>   ppc: Remove MMU_MODEn_SUFFIX definitions
>   ppc: Use split I/D mmu modes to avoid flushes on interrupts
>   ppc: Do some batching of TCG tlb flushes
>   ppc: Add a bunch of hypervisor SPRs to Book3s
>   ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
>   ppc: Fix rfi/rfid/hrfi/... emulation
>   ppc: Better figure out if processor has HV mode
>   ppc: tlbie, tlbia and tlbisync are HV only
>   ppc: Change 'invalid' bit mask of tlbiel and tlbie
>   ppc: Get out of emulation on SMT "OR" ops
>   ppc: Add PPC_64H instruction flag to POWER7 and POWER8
> 
> Michael Neuling (1):
>   ppc: Fix sign extension issue in mtmsr(d) emulation
> 
>  hw/ppc/spapr_hcall.c        |  14 ++++-
>  target-ppc/cpu.h            |  20 ++++--
>  target-ppc/excp_helper.c    |  77 +++++++++++------------
>  target-ppc/helper.h         |   1 +
>  target-ppc/helper_regs.h    |  71 +++++++++++++++++++---
>  target-ppc/machine.c        |   5 +-
>  target-ppc/mmu-hash64.c     |  11 +---
>  target-ppc/mmu_helper.c     |   9 ++-
>  target-ppc/translate.c      |  94 +++++++++++++++++++++++------
>  target-ppc/translate_init.c | 144 
> +++++++++++++++++++++++++++++++++++++++++---
>  10 files changed, 348 insertions(+), 98 deletions(-)
> 

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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