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[Qemu-devel] [PULL 34/43] target-arm: Avoid unnecessary TLB flush on TCR
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 34/43] target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writes |
Date: |
Thu, 12 May 2016 14:32:56 +0100 |
The TCR_EL2 and TCR_EL3 regdefs were incorrectly using the
vmsa_tcr_el1_write function for writes. Since these registers don't
have the A1 bit that TCR_EL1 does, we don't need to do a tlb_flush()
when they are written. Remove the unnecessary .writefn and also the
harmless but unneeded .raw_writefn and .resetfn definitions.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
---
target-arm/helper.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3b76dc3..a2ab701 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3559,8 +3559,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.resetvalue = 0 },
{ .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
- .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
- .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
+ .access = PL2_RW,
+ /* no .writefn needed as this can't cause an ASID change;
+ * no .raw_writefn or .resetfn needed as we never use mask/base_mask
+ */
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
{ .name = "VTCR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
@@ -3753,8 +3755,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
{ .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
- .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
- .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
+ .access = PL3_RW,
+ /* no .writefn needed as this can't cause an ASID change;
+ * no .raw_writefn or .resetfn needed as we never use mask/base_mask
+ */
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
{ .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_ALIAS,
--
1.9.1
- [Qemu-devel] [PULL 16/43] gen-icount: Use tcg_set_insn_param, (continued)
- [Qemu-devel] [PULL 16/43] gen-icount: Use tcg_set_insn_param, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 28/43] FIFO: Add a FIFO32 implementation, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 32/43] hw/display/blizzard: Expand out macros, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 25/43] ACPI: Virt: Generate SRAT table, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 37/43] hw/arm: QOM'ify integratorcp.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 03/43] hw/intc: QOM'ify etraxfs_pic.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 39/43] hw/arm: QOM'ify pxa2xx_pic.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 33/43] hw/display/blizzard: Remove blizzard_template.h, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 38/43] hw/arm: QOM'ify pxa2xx.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 10/43] hw/intc: QOM'ify omap_intc.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 34/43] target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writes,
Peter Maydell <=
- [Qemu-devel] [PULL 36/43] hw/arm: QOM'ify highbank.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 43/43] hw/arm: QOM'ify versatilepb.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 41/43] hw/arm: QOM'ify stellaris.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 26/43] ARM: Factor out ARM on/off PSCI control functions, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 09/43] hw/intc: QOM'ify grlib_irqmp.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 21/43] ARM: Virt: Set numa-node-id for cpu and memory nodes, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 30/43] i.MX: Add i.MX6 SOC implementation., Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 42/43] hw/arm: QOM'ify strongarm.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 40/43] hw/arm: QOM'ify spitz.c, Peter Maydell, 2016/05/12
- Re: [Qemu-devel] [PULL 00/43] target-arm queue, Peter Maydell, 2016/05/12