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[Qemu-devel] [PULL 17/43] target-arm: Split data abort syndrome generato
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/43] target-arm: Split data abort syndrome generator |
Date: |
Thu, 12 May 2016 14:32:39 +0100 |
Split the data abort syndrome generator into two versions:
One with a valid Instruction Specific Syndrome (ISS) and another without.
The following new flags are supported by the syndrome generator
with ISS:
* isv - Instruction syndrome valid
* sas - Syndrome access size
* sse - Syndrome sign extend
* srt - Syndrome register transfer
* sf - Sixty-Four bit register width
* ar - Acquire/Release
These flags are not yet used, so this patch has no functional change
except that we will now correctly set the IL bit in data abort
syndromes without ISS information.
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden>
[PMM: squashed in with patch which was just adding the IL bit]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/internals.h | 24 +++++++++++++++++++++---
target-arm/op_helper.c | 6 ++++--
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/target-arm/internals.h b/target-arm/internals.h
index 2e70272..54a0fb1 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -263,7 +263,9 @@ enum arm_exception_class {
#define ARM_EL_EC_SHIFT 26
#define ARM_EL_IL_SHIFT 25
+#define ARM_EL_ISV_SHIFT 24
#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
+#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
/* Utility functions for constructing various kinds of syndrome value.
* Note that in general we follow the AArch64 syndrome values; in a
@@ -383,11 +385,27 @@ static inline uint32_t syn_insn_abort(int same_el, int
ea, int s1ptw, int fsc)
| (ea << 9) | (s1ptw << 7) | fsc;
}
-static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
- int wnr, int fsc)
+static inline uint32_t syn_data_abort_no_iss(int same_el,
+ int ea, int cm, int s1ptw,
+ int wnr, int fsc)
{
return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
- | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
+ | ARM_EL_IL
+ | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
+}
+
+static inline uint32_t syn_data_abort_with_iss(int same_el,
+ int sas, int sse, int srt,
+ int sf, int ar,
+ int ea, int cm, int s1ptw,
+ int wnr, int fsc,
+ bool is_16bit)
+{
+ return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
+ | (is_16bit ? 0 : ARM_EL_IL)
+ | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
+ | (sf << 15) | (ar << 14)
+ | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
}
static inline uint32_t syn_swstep(int same_el, int isv, int ex)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index d626ff1..c7fba85 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -115,7 +115,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
is_write, int mmu_idx,
syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
exc = EXCP_PREFETCH_ABORT;
} else {
- syn = syn_data_abort(same_el, 0, 0, fi.s1ptw, is_write == 1, syn);
+ syn = syn_data_abort_no_iss(same_el,
+ 0, 0, fi.s1ptw, is_write == 1, syn);
if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) {
fsr |= (1 << 11);
}
@@ -161,7 +162,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
int is_write,
}
raise_exception(env, EXCP_DATA_ABORT,
- syn_data_abort(same_el, 0, 0, 0, is_write == 1, 0x21),
+ syn_data_abort_no_iss(same_el,
+ 0, 0, 0, is_write == 1, 0x21),
target_el);
}
--
1.9.1
- [Qemu-devel] [PULL 00/43] target-arm queue, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 19/43] target-arm/translate-a64.c: Unify some of the ldst_reg decoding, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 02/43] omap_lcdc: Remove support for DEPTH != 32, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 12/43] hw/arm/nseries: Allocating Large sized arrays to heap, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 17/43] target-arm: Split data abort syndrome generator,
Peter Maydell <=
- [Qemu-devel] [PULL 07/43] hw/intc: QOM'ify pl190.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 05/43] hw/intc: QOM'ify exynos4210_gic.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 18/43] target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 01/43] blizzard: Remove support for DEPTH != 32, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 13/43] target-arm: Stage 2 permission fault was fixed in AArch32 state, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 11/43] bcm2835_property: use cached values when querying framebuffer, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 06/43] hw/intc: QOM'ify imx_avic.c, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 15/43] tcg: Add tcg_set_insn_param, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 23/43] ACPI: Fix the definition of proximity in AcpiSratMemoryAffinity, Peter Maydell, 2016/05/12
- [Qemu-devel] [PULL 31/43] i.MX: Add sabrelite i.MX6 emulation., Peter Maydell, 2016/05/12