[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v6 01/26] acpi: enable INTR for DMAR report structur
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v6 01/26] acpi: enable INTR for DMAR report structure |
Date: |
Thu, 5 May 2016 11:25:36 +0800 |
Introduce iommu_intr in MachineState to show whether IOMMU IR is
enabled. By default, IR is off.
In ACPI DMA remapping report structure, enable INTR flag when specified.
Signed-off-by: Peter Xu <address@hidden>
---
hw/core/machine.c | 2 ++
hw/i386/acpi-build.c | 12 +++++++++---
include/hw/boards.h | 1 +
include/hw/i386/intel_iommu.h | 2 ++
4 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 6dbbc85..276ad61 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -382,6 +382,8 @@ static void machine_initfn(Object *obj)
ms->kvm_shadow_mem = -1;
ms->dump_guest_core = true;
ms->mem_merge = true;
+ /* Disable interrupt remapping by default. */
+ ms->iommu_intr = false;
object_property_add_str(obj, "accel",
machine_get_accel, machine_set_accel, NULL);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 6477003..80dd1bb 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2575,16 +2575,22 @@ build_mcfg_q35(GArray *table_data, GArray *linker,
AcpiMcfgInfo *info)
}
static void
-build_dmar_q35(GArray *table_data, GArray *linker)
+build_dmar_q35(MachineState *ms, GArray *table_data, GArray *linker)
{
int dmar_start = table_data->len;
AcpiTableDmar *dmar;
AcpiDmarHardwareUnit *drhd;
+ uint8_t dmar_flags = 0;
+
+ if (ms->iommu_intr) {
+ /* enable INTR for the IOMMU device */
+ dmar_flags |= DMAR_REPORT_F_INTR;
+ }
dmar = acpi_data_push(table_data, sizeof(*dmar));
dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
- dmar->flags = 0; /* No intr_remap for now */
+ dmar->flags = dmar_flags;
/* DMAR Remapping Hardware Unit Definition structure */
drhd = acpi_data_push(table_data, sizeof(*drhd));
@@ -2745,7 +2751,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState
*machine)
}
if (acpi_has_iommu()) {
acpi_add_table(table_offsets, tables_blob);
- build_dmar_q35(tables_blob, tables->linker);
+ build_dmar_q35(MACHINE(pcms), tables_blob, tables->linker);
}
if (pcms->acpi_nvdimm_state.is_enabled) {
nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 8d4fe56..43f4976 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -152,6 +152,7 @@ struct MachineState {
bool igd_gfx_passthru;
char *firmware;
bool iommu;
+ bool iommu_intr;
bool suppress_vmdesc;
bool enforce_config_section;
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index b024ffa..0d89796 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -44,6 +44,8 @@
#define VTD_HOST_ADDRESS_WIDTH 39
#define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1)
+#define DMAR_REPORT_F_INTR (1)
+
typedef struct VTDContextEntry VTDContextEntry;
typedef struct VTDContextCacheEntry VTDContextCacheEntry;
typedef struct IntelIOMMUState IntelIOMMUState;
--
2.4.11
- [Qemu-devel] [PATCH v6 00/26] IOMMU: Enable interrupt remapping for Intel IOMMU, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 01/26] acpi: enable INTR for DMAR report structure,
Peter Xu <=
- [Qemu-devel] [PATCH v6 02/26] intel_iommu: allow queued invalidation for IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 03/26] intel_iommu: set IR bit for ECAP register, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 04/26] acpi: add DMAR scope definition for root IOAPIC, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 05/26] intel_iommu: define interrupt remap table addr register, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 06/26] intel_iommu: handle interrupt remap enable, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 07/26] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 08/26] intel_iommu: provide helper function vtd_get_iommu, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 09/26] intel_iommu: add IR translation faults defines, Peter Xu, 2016/05/04