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[Qemu-devel] [PATCH 23/52] target-m68k: Use setcond for scc
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH 23/52] target-m68k: Use setcond for scc |
Date: |
Wed, 4 May 2016 22:12:03 +0200 |
From: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index efd4d9c..332c34f 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -862,19 +862,21 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel
*l1)
DISAS_INSN(scc)
{
- TCGLabel *l1;
+ DisasCompare c;
int cond;
- TCGv reg;
+ TCGv reg, tmp;
- l1 = gen_new_label();
cond = (insn >> 8) & 0xf;
+ gen_cc_cond(&c, s, cond);
+
+ tmp = tcg_temp_new();
+ tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
+ free_cond(&c);
+
reg = DREG(insn, 0);
- tcg_gen_andi_i32(reg, reg, 0xffffff00);
- /* This is safe because we modify the reg directly, with no other values
- live. */
- gen_jmpcc(s, cond ^ 1, l1);
- tcg_gen_ori_i32(reg, reg, 0xff);
- gen_set_label(l1);
+ tcg_gen_neg_i32(tmp, tmp);
+ tcg_gen_deposit_i32(reg, reg, tmp, 0, 8);
+ tcg_temp_free(tmp);
}
/* Force a TB lookup after an instruction that changes the CPU state. */
--
2.5.5
- [Qemu-devel] [PATCH 17/52] target-m68k: Print flags properly, (continued)
- [Qemu-devel] [PATCH 17/52] target-m68k: Print flags properly, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 16/52] target-m68k: update CPU flags management, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 18/52] target-m68k: Some fixes to SR and flags management, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 20/52] target-m68k: Remove incorrect clearing of cc_x, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 19/52] target-m68k: terminate cpu dump with newline, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 22/52] target-m68k: Introduce DisasCompare, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 23/52] target-m68k: Use setcond for scc,
Laurent Vivier <=
- [Qemu-devel] [PATCH 21/52] target-m68k: Reorg flags handling, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 24/52] target-m68k: Optimize some comparisons, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 25/52] target-m68k: Optimize gen_flush_flags, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 26/52] target-m68k: Inline shifts, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 27/52] target-m68k: Inline addx, subx, negx, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 28/52] target-m68k: add addx/subx/negx ops, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 29/52] target-m68k: factorize flags computing, Laurent Vivier, 2016/05/04