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[Qemu-devel] [PATCH v5 18/18] ioapic: clear remote irr bit for edge-trig
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v5 18/18] ioapic: clear remote irr bit for edge-triggered interrupts |
Date: |
Thu, 28 Apr 2016 15:05:44 +0800 |
This is to better emulate IOAPIC version 0x1X hardware. Linux kernel
leveraged this "feature" to do explicit EOI since EOI register is still
not introduced at that time. This will also fix the issue that level
triggered interrupts failed to work when IR enabled (tested with Linux
kernel version 4.5).
Signed-off-by: Peter Xu <address@hidden>
---
hw/intc/ioapic.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index d7ebb5c..ce06954 100644
--- a/hw/intc/ioapic.c
+++ b/hw/intc/ioapic.c
@@ -281,6 +281,34 @@ ioapic_mem_read(void *opaque, hwaddr addr, unsigned int
size)
return val;
}
+/*
+ * This is to satisfy the hack in Linux kernel. One hack of it is to
+ * simulate clearing the Remote IRR bit of IOAPIC entry using the
+ * following:
+ *
+ * "For IO-APIC's with EOI register, we use that to do an explicit EOI.
+ * Otherwise, we simulate the EOI message manually by changing the trigger
+ * mode to edge and then back to level, with RTE being masked during
+ * this."
+ *
+ * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701)
+ *
+ * This is based on the assumption that, Remote IRR bit will be
+ * cleared by IOAPIC hardware when configured as edge-triggered
+ * interrupts.
+ *
+ * Without this, level-triggered interrupts in IR mode might fail to
+ * work correctly.
+ */
+static inline void
+ioapic_fix_edge_remote_irr(uint64_t *entry)
+{
+ if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) {
+ /* Edge-triggered interrupts, make sure remote IRR is zero */
+ *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR);
+ }
+}
+
static void
ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int size)
@@ -318,6 +346,7 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
/* restore RO bits */
s->ioredtbl[index] &= IOAPIC_RW_BITS;
s->ioredtbl[index] |= ro_bits;
+ ioapic_fix_edge_remote_irr(&s->ioredtbl[index]);
ioapic_service(s);
}
}
--
2.4.3
- [Qemu-devel] [PATCH v5 15/18] intel_iommu: introduce IEC notifiers, (continued)
- [Qemu-devel] [PATCH v5 15/18] intel_iommu: introduce IEC notifiers, Peter Xu, 2016/04/28
- Re: [Qemu-devel] [PATCH v5 15/18] intel_iommu: introduce IEC notifiers, Jan Kiszka, 2016/04/28
- Re: [Qemu-devel] [PATCH v5 15/18] intel_iommu: introduce IEC notifiers, Peter Xu, 2016/04/28
- Re: [Qemu-devel] [PATCH v5 15/18] intel_iommu: introduce IEC notifiers, Jan Kiszka, 2016/04/28
- Re: [Qemu-devel] [PATCH v5 15/18] intel_iommu: introduce IEC notifiers, Peter Xu, 2016/04/28
- Re: [Qemu-devel] [PATCH v5 15/18] intel_iommu: introduce IEC notifiers, David Kiarie, 2016/04/28
- Re: [Qemu-devel] [PATCH v5 15/18] intel_iommu: introduce IEC notifiers, Peter Xu, 2016/04/28
[Qemu-devel] [PATCH v5 16/18] ioapic: register VT-d IEC invalidate notifier, Peter Xu, 2016/04/28
[Qemu-devel] [PATCH v5 17/18] ioapic: keep RO bits for IOAPIC entry, Peter Xu, 2016/04/28
[Qemu-devel] [PATCH v5 18/18] ioapic: clear remote irr bit for edge-triggered interrupts,
Peter Xu <=
Re: [Qemu-devel] [PATCH v5 00/18] IOMMU: Enable interrupt remapping for Intel IOMMU, Peter Xu, 2016/04/28
Re: [Qemu-devel] [PATCH v5 00/18] IOMMU: Enable interrupt remapping for Intel IOMMU, Jan Kiszka, 2016/04/28
[Qemu-devel] [PATCH 19/18] intel_iommu: Add support for Extended Interrupt Mode, Jan Kiszka, 2016/04/28