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[Qemu-devel] [PULL 5/5] target-arm: Make the 64-bit version of VTCR do t
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 5/5] target-arm: Make the 64-bit version of VTCR do the migration |
Date: |
Mon, 4 Apr 2016 17:43:12 +0100 |
Move the ALIAS tag from VTCR_EL2 to VTCR so that we migrate the
64-bit version, as is usual. (This has no particular effect now
unless the guest wrote to the high RES0 bits of VTCR_EL2.)
Add a comment about why it's OK that we don't have the various
accessor functions that the EL1 TCR regdefs do.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 0e54d90..09638b2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3564,11 +3564,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
{ .name = "VTCR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
+ .type = ARM_CP_ALIAS,
.access = PL2_RW, .accessfn = access_el3_aa32ns,
.fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
{ .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
- .access = PL2_RW, .type = ARM_CP_ALIAS,
+ .access = PL2_RW,
+ /* no .writefn needed as this can't cause an ASID change;
+ * no .raw_writefn or .resetfn needed as we never use mask/base_mask
+ */
.fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
{ .name = "VTTBR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 6, .crm = 2,
--
1.9.1
- [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2016/04/04
- [Qemu-devel] [PULL 5/5] target-arm: Make the 64-bit version of VTCR do the migration,
Peter Maydell <=
- [Qemu-devel] [PULL 3/5] target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUs, Peter Maydell, 2016/04/04
- [Qemu-devel] [PULL 4/5] target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3, Peter Maydell, 2016/04/04
- [Qemu-devel] [PULL 1/5] hw/arm/bcm2836: Wire up CPU timer interrupts correctly, Peter Maydell, 2016/04/04
- [Qemu-devel] [PULL 2/5] linux-user: arm: Handle (ignore) EXCP_YIELD in ARM cpu_loop(), Peter Maydell, 2016/04/04
- Re: [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2016/04/05