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[Qemu-devel] [PULL 07/16] target-i386: Perform set/reset_inhibit_irq inl
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 07/16] target-i386: Perform set/reset_inhibit_irq inline |
Date: |
Mon, 15 Feb 2016 22:23:19 +1100 |
With helpers that can be reused for other things.
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/cc_helper.c | 10 ----------
target-i386/helper.h | 2 --
target-i386/translate.c | 37 ++++++++++++++++++++++++++++---------
3 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/target-i386/cc_helper.c b/target-i386/cc_helper.c
index 99a3b54..83af223 100644
--- a/target-i386/cc_helper.c
+++ b/target-i386/cc_helper.c
@@ -383,13 +383,3 @@ void helper_sti_vm(CPUX86State *env)
}
}
#endif
-
-void helper_set_inhibit_irq(CPUX86State *env)
-{
- env->hflags |= HF_INHIBIT_IRQ_MASK;
-}
-
-void helper_reset_inhibit_irq(CPUX86State *env)
-{
- env->hflags &= ~HF_INHIBIT_IRQ_MASK;
-}
diff --git a/target-i386/helper.h b/target-i386/helper.h
index 9a83955..14a5041 100644
--- a/target-i386/helper.h
+++ b/target-i386/helper.h
@@ -62,8 +62,6 @@ DEF_HELPER_1(cli, void, env)
DEF_HELPER_1(sti, void, env)
DEF_HELPER_1(clac, void, env)
DEF_HELPER_1(stac, void, env)
-DEF_HELPER_1(set_inhibit_irq, void, env)
-DEF_HELPER_1(reset_inhibit_irq, void, env)
DEF_HELPER_3(boundw, void, env, tl, int)
DEF_HELPER_3(boundl, void, env, tl, int)
DEF_HELPER_1(rsm, void, env)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index dc87e58..cb25354 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2391,14 +2391,36 @@ static void gen_debug(DisasContext *s, target_ulong
cur_eip)
s->is_jmp = DISAS_TB_JUMP;
}
+static void gen_set_hflag(DisasContext *s, uint32_t mask)
+{
+ if ((s->flags & mask) == 0) {
+ TCGv_i32 t = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_gen_ori_i32(t, t, mask);
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_temp_free_i32(t);
+ s->flags |= mask;
+ }
+}
+
+static void gen_reset_hflag(DisasContext *s, uint32_t mask)
+{
+ if (s->flags & mask) {
+ TCGv_i32 t = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_gen_andi_i32(t, t, ~mask);
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
+ tcg_temp_free_i32(t);
+ s->flags &= ~mask;
+ }
+}
+
/* generate a generic end of block. Trace exception is also generated
if needed */
static void gen_eob(DisasContext *s)
{
gen_update_cc_op(s);
- if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
- gen_helper_reset_inhibit_irq(cpu_env);
- }
+ gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK);
if (s->tb->flags & HF_RF_MASK) {
gen_helper_reset_rf(cpu_env);
}
@@ -5147,8 +5169,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
/* if reg == SS, inhibit interrupts/trace. */
/* If several instructions disable interrupts, only the
_first_ does it */
- if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
- gen_helper_set_inhibit_irq(cpu_env);
+ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
s->tf = 0;
}
if (s->is_jmp) {
@@ -5215,8 +5236,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
/* if reg == SS, inhibit interrupts/trace */
/* If several instructions disable interrupts, only the
_first_ does it */
- if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
- gen_helper_set_inhibit_irq(cpu_env);
+ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
s->tf = 0;
}
if (s->is_jmp) {
@@ -6752,8 +6772,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
/* interruptions are enabled only the first insn after sti */
/* If several instructions disable interrupts, only the
_first_ does it */
- if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
- gen_helper_set_inhibit_irq(cpu_env);
+ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK);
/* give a chance to handle pending irqs */
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
--
2.5.0
- [Qemu-devel] [PULL 00/16] target-i386: xsave, mpx, fsgsbase extensions, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 01/16] target-i386: Split fxsave/fxrstor implementation, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 02/16] target-i386: Rearrange processing of 0F 01, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 03/16] target-i386: Rearrange processing of 0F AE, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 04/16] target-i386: Add XSAVE extension, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 05/16] target-i386: Implement XSAVEOPT, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 06/16] target-i386: Enable control registers for MPX, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 07/16] target-i386: Perform set/reset_inhibit_irq inline,
Richard Henderson <=
- [Qemu-devel] [PULL 08/16] target-i386: Split up gen_lea_modrm, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 09/16] target-i386: Implement BNDMK, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 12/16] target-i386: Update BNDSTATUS for exceptions raised by BOUND, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 10/16] target-i386: Implement BNDMOV, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 11/16] target-i386: Implement BNDCL, BNDCU, BNDCN, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 13/16] target-i386: Implement BNDLDX, BNDSTX, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 14/16] target-i386: Clear bndregs during legacy near jumps, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 15/16] target-i386: Enable CR4/XCR0 features for user-mode, Richard Henderson, 2016/02/15
- [Qemu-devel] [PULL 16/16] target-i386: Implement FSGSBASE, Richard Henderson, 2016/02/15
- Re: [Qemu-devel] [PULL 00/16] target-i386: xsave, mpx, fsgsbase extensions, Peter Maydell, 2016/02/15