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[Qemu-devel] [PATCH 2/5] target-tricore: Save the pc before CSA operatio
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH 2/5] target-tricore: Save the pc before CSA operations for exceptions |
Date: |
Thu, 11 Feb 2016 17:01:57 +0100 |
Exceptions that can occur during CSA operations need the PC as
the return address of the exception.
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/translate.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 721878d..775d4c6 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3336,6 +3336,8 @@ static void gen_compute_branch(DisasContext *ctx,
uint32_t opc, int r1,
break;
case OPC1_32_B_CALL:
case OPC1_16_SB_CALL:
+ /* save pc for the exception return address */
+ gen_save_pc(ctx->pc);
gen_helper_1arg(call, ctx->next_pc);
gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
break;
@@ -3408,6 +3410,8 @@ static void gen_compute_branch(DisasContext *ctx,
uint32_t opc, int r1,
break;
case OPC2_32_SYS_RET:
case OPC2_16_SR_RET:
+ /* save pc for the exception return address */
+ gen_save_pc(ctx->pc);
gen_helper_ret(cpu_env);
tcg_gen_exit_tb(0);
break;
@@ -3782,6 +3786,8 @@ static void decode_sc_opc(DisasContext *ctx, int op1)
tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
break;
case OPC1_16_SC_BISR:
+ /* save pc for the exception return address */
+ gen_save_pc(ctx->pc);
gen_helper_1arg(bisr, const16 & 0xff);
break;
case OPC1_16_SC_LD_A:
@@ -3897,6 +3903,8 @@ static void decode_sr_system(CPUTriCoreState *env,
DisasContext *ctx)
gen_compute_branch(ctx, op2, 0, 0, 0, 0);
break;
case OPC2_16_SR_RFE:
+ /* save pc for the exception return address */
+ gen_save_pc(ctx->pc);
gen_helper_rfe(cpu_env);
tcg_gen_exit_tb(0);
ctx->bstate = BS_BRANCH;
@@ -7895,6 +7903,8 @@ static void decode_sys_interrupts(CPUTriCoreState *env,
DisasContext *ctx)
gen_fret(ctx);
break;
case OPC2_32_SYS_RFE:
+ /* save pc for the exception return address */
+ gen_save_pc(ctx->pc);
gen_helper_rfe(cpu_env);
tcg_gen_exit_tb(0);
ctx->bstate = BS_BRANCH;
@@ -7917,9 +7927,13 @@ static void decode_sys_interrupts(CPUTriCoreState *env,
DisasContext *ctx)
}
break;
case OPC2_32_SYS_RSLCX:
+ /* save pc for the exception return address */
+ gen_save_pc(ctx->pc);
gen_helper_rslcx(cpu_env);
break;
case OPC2_32_SYS_SVLCX:
+ /* save pc for the exception return address */
+ gen_save_pc(ctx->pc);
gen_helper_svlcx(cpu_env);
break;
case OPC2_32_SYS_RESTORE:
--
2.7.1