[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 2/3] target-arm: Fix IL bit reported for Thumb c
From: |
Sergey Fedorov |
Subject: |
Re: [Qemu-devel] [PATCH 2/3] target-arm: Fix IL bit reported for Thumb coprocessor traps |
Date: |
Sat, 6 Feb 2016 21:24:27 +0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 |
On 05.02.2016 17:37, Peter Maydell wrote:
> All Thumb coprocessor instructions are 32 bits, so the IL
> bit in the syndrome register should be set. Pass false to the
> syn_* function's is_16bit argument rather than s->thumb
> so we report the correct IL bit.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
> ---
> target-arm/translate.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 3ec758a..10792e8 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -7184,19 +7184,19 @@ static int disas_coproc_insn(DisasContext *s,
> uint32_t insn)
> case 14:
> if (is64) {
> syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
> - isread, s->thumb);
> + isread, false);
> } else {
> syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
> - rt, isread, s->thumb);
> + rt, isread, false);
> }
> break;
> case 15:
> if (is64) {
> syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
> - isread, s->thumb);
> + isread, false);
> } else {
> syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
> - rt, isread, s->thumb);
> + rt, isread, false);
> }
> break;
> default: