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[Qemu-devel] [PATCH v2 3/5] target-arm: Add the pmovsclr_el0 and pminten
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v2 3/5] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers |
Date: |
Fri, 5 Feb 2016 16:55:21 -0800 |
Signed-off-by: Aaron Lindsay <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Tested-by: Nathan Rossi <address@hidden>
---
target-arm/helper.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 164853f..8d401c6 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1031,6 +1031,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.accessfn = pmreg_access,
.writefn = pmovsr_write,
.raw_writefn = raw_write },
+ { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
+ .access = PL0_RW, .accessfn = pmreg_access,
+ .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
+ .writefn = pmovsr_write,
+ .raw_writefn = raw_write },
/* Unimplemented so WI. */
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
.access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
@@ -1096,6 +1103,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_RW, .type = ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
.writefn = pmintenclr_write, },
+ { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
+ .writefn = pmintenclr_write },
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
--
2.5.0
- [Qemu-devel] [PATCH v2 1/5] target-arm: Add the pmceid0 and pmceid1 registers, (continued)
[Qemu-devel] [PATCH v2 2/5] target-arm: Add Some of the performance monitor registers, Alistair Francis, 2016/02/05
[Qemu-devel] [PATCH v2 3/5] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers,
Alistair Francis <=
[Qemu-devel] [PATCH v2 4/5] target-arm: Add PMUSERENR_EL0 register, Alistair Francis, 2016/02/05
[Qemu-devel] [PATCH v2 5/5] target-arm: Unmask PMU bits in debug feature register, Alistair Francis, 2016/02/05