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Re: [Qemu-devel] [PATCH 5/7] target-arm: Add isread parameter to CPAcces
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 5/7] target-arm: Add isread parameter to CPAccessFns |
Date: |
Fri, 5 Feb 2016 14:29:21 +0000 |
On 5 February 2016 at 14:20, Alex Bennée <address@hidden> wrote:
>
> Peter Maydell <address@hidden> writes:
>> -typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo
>> *opaque);
>> +typedef CPAccessResult CPAccessFn(CPUARMState *env,
>> + const ARMCPRegInfo *opaque,
>> + bool isread);
>
> I guess my only comment here is we've extended the call for every access
> check with another parameter (and associated TCG activity) for something
> only one handler currently cares about.
>
> Is there an argument for an rwaccessfn() that we use for just those
> registers that care about the detail? I know system registers are hardly
> a fast path priority but I'm concerned about knock on effects on
> performance. Have you done any measurements?
I haven't measured, no, but since there are only 3 arguments the
third argument is going to be in a register on any host architecture
we care about, which means the overhead is just going to be a single
"load constant 0 or 1 into register before the call". I think that's
going to be lost in the noise compared to actually having to make
the function call at all, the work the function call does, and then
the second function call later to do the read or write.
thanks
-- PMM
- Re: [Qemu-devel] [PATCH 7/7] target-arm: Enable EL3 for Cortex-A53 and Cortex-A57, (continued)
Re: [Qemu-devel] [PATCH 5/7] target-arm: Add isread parameter to CPAccessFns, Edgar E. Iglesias, 2016/02/06
Re: [Qemu-devel] [PATCH 5/7] target-arm: Add isread parameter to CPAccessFns, Sergey Fedorov, 2016/02/06
[Qemu-devel] [PATCH 6/7] target-arm: Implement NSACR trapping behaviour, Peter Maydell, 2016/02/03
[Qemu-devel] [PATCH 1/7] target-arm: Fix typo in comment in arm_is_secure_below_el3(), Peter Maydell, 2016/02/03