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[Qemu-devel] [PATCH 7/9] hw/mips_malta: make ITU available to multi-thre
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH 7/9] hw/mips_malta: make ITU available to multi-threading processors |
Date: |
Wed, 3 Feb 2016 16:56:49 +0000 |
Add ITU block to Malta board and make it available to multithreading
processors.
Signed-off-by: Leon Alrae <address@hidden>
---
hw/mips/mips_malta.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index c5da83f..2c54a04 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -55,6 +55,7 @@
#include "hw/empty_slot.h"
#include "sysemu/kvm.h"
#include "exec/semihost.h"
+#include "hw/misc/mips_itu.h"
//#define DEBUG_BOARD_INIT
@@ -93,6 +94,7 @@ typedef struct {
typedef struct {
SysBusDevice parent_obj;
+ MIPSITUState itu;
qemu_irq *i8259;
} MaltaState;
@@ -567,6 +569,25 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion
*address_space,
return s;
}
+static void itu_init(MaltaState *s, Error **err)
+{
+ SysBusDevice *itubusdev;
+
+ object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU);
+ qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default());
+
+ object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", err);
+ object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", err);
+ object_property_set_bool(OBJECT(&s->itu), true, "realized", err);
+
+ if (*err != NULL) {
+ return;
+ }
+
+ itubusdev = SYS_BUS_DEVICE(&s->itu);
+ sysbus_mmio_map_overlap(itubusdev, 0, 0, 1);
+}
+
/* Network support */
static void network_init(PCIBus *pci_bus)
{
@@ -882,6 +903,10 @@ static void malta_mips_config(MIPSCPU *cpu)
env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC);
+
+ if (env->itc_tag) {
+ env->mvp->CP0_MVPConf0 |= 1 << CP0MVPC0_GS;
+ }
}
static void main_cpu_reset(void *opaque)
@@ -906,6 +931,20 @@ static void main_cpu_reset(void *opaque)
}
}
+static bool cpu_mips_itu_supported(CPUMIPSState *env)
+{
+ bool is_mt = ((env->CP0_Config5 & (1 << CP0C5_VP)) != 0) ||
+ ((env->CP0_Config3 & (1 << CP0C3_MT)) != 0);
+
+ return is_mt && !kvm_enabled();
+
+}
+
+static void cpu_mips_attach_itc_tag(CPUMIPSState *env, MIPSITUState *itu)
+{
+ env->itc_tag = mips_itu_get_tag_region(itu);
+}
+
static
void mips_malta_init(MachineState *machine)
{
@@ -940,6 +979,7 @@ void mips_malta_init(MachineState *machine)
int fl_idx = 0;
int fl_sectors = bios_size >> 16;
int be;
+ bool itu_present = false;
DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA);
MaltaState *s = MIPS_MALTA(dev);
@@ -980,6 +1020,10 @@ void mips_malta_init(MachineState *machine)
/* Init internal devices */
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
+ if (cpu_mips_itu_supported(env)) {
+ itu_present = true;
+ cpu_mips_attach_itc_tag(env, &s->itu);
+ }
qemu_register_reset(main_cpu_reset, cpu);
}
cpu = MIPS_CPU(first_cpu);
@@ -1137,6 +1181,15 @@ void mips_malta_init(MachineState *machine)
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
+ if (itu_present) {
+ Error *err = NULL;
+ itu_init(s, &err);
+ if (err != NULL) {
+ error_report("%s", error_get_pretty(err));
+ exit(1);
+ }
+ }
+
/*
* We have a circular dependency problem: pci_bus depends on isa_irq,
* isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
--
2.1.0
- [Qemu-devel] [PATCH 0/9] mips: implement Inter-Thread Communication Unit, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 1/9] hw/mips: implement ITC Configuration Tags, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 2/9] hw/mips: add ITC Storage Cells, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 3/9] hw/mips: implement ITC Storage - Control View, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 4/9] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 5/9] hw/mips: implement ITC Storage - P/V Sync and Try Views, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 8/9] target-mips: check CP0 enabled for CACHE instruction also in R6, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 6/9] hw/mips: implement ITC Storage - Bypass View, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 7/9] hw/mips_malta: make ITU available to multi-threading processors,
Leon Alrae <=
- [Qemu-devel] [PATCH 9/9] target-mips: make ITC Configuration Tags accessible to the CPU, Leon Alrae, 2016/02/03