[Qemu-devel] [PATCHv2 00/10] Clean up page size handling for ppc 64-bit hash MMUs with TCG

[David Gibson]

Encoding of page sizes on 64-bit hash MMUs for Power is rather arcane,
involving control bits in both the SLB and HPTE.  At present we
support a few of the options, but far fewer than real hardware.

We're able to get away with that in practice, because guests use a
device tree property to determine which page sizes are available and
we are setting that to match.  However, the fact that the actual code
doesn't necessarily what we put into the table of available page sizes
is another ugliness.

This series makes a number of cleanups to the page size handling.  The
upshot is that afterwards the softmmu code operates off the same page
size encoding table that is advertised to the guests, ensuring that
they will be in sync.

Finally, we extend the table of allowed sizes for POWER7 and POWER8 to
include the options allowed in hardware (including MPSS).  We can fix
other hash MMU based CPUs in future if anyone cares enough.

For a simple benchmark I timed fully booting then cleanly shutting
down a TCG guest (RHEL7.2 userspace with a recent upstream kernel).
Repeated 5 times on the current master branch, my current ppc-for-2.6
branch and this branch.  It looks like it improves speed, although the
difference is pretty much negligible:

master:         2m25 2m28 2m26 2m26 2m26
ppc-for-2.6:    2m26 2m25 2m26 2m27 2m25
this series:    2m20 2m23 2m23 2m25 2m21

Please review, and I'll fold into ppc-for-2.6 for my next pull.

Changes since v1:
  * Fix a couple of simple but serious bugs in logic
  * Did some rudimentary benchmarking
Changes since RFC:
  * Moved lookup of SLB encodings table from SLB lookup time to SLB
      store time

David Gibson (10):
  target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub
  target-ppc: Convert mmu-hash{32,64}.[ch] from CPUPPCState to
    PowerPCCPU
  target-ppc: Rework ppc_store_slb
  target-ppc: Rework SLB page size lookup
  target-ppc: Use actual page size encodings from HPTE
  target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one
  target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one()
  target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs
  target-ppc: Helper to determine page size information from hpte alone
  target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG

 hw/ppc/spapr_hcall.c        | 102 ++++-------------
 target-ppc/cpu.h            |   1 +
 target-ppc/helper.h         |   1 +
 target-ppc/kvm.c            |   2 +-
 target-ppc/kvm_ppc.h        |   5 -
 target-ppc/machine.c        |  20 ++++
 target-ppc/mmu-hash32.c     |  68 ++++++-----
 target-ppc/mmu-hash32.h     |  30 ++---
 target-ppc/mmu-hash64.c     | 270 +++++++++++++++++++++++++++++++-------------
 target-ppc/mmu-hash64.h     |  30 +++--
 target-ppc/mmu_helper.c     |  59 ++++------
 target-ppc/translate.c      |   2 +-
 target-ppc/translate_init.c |  32 ++++++
 13 files changed, 372 insertions(+), 250 deletions(-)

-- 
2.5.0