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[Qemu-devel] [V4 0/4] AMD IO MMU
From: |
David Kiarie |
Subject: |
[Qemu-devel] [V4 0/4] AMD IO MMU |
Date: |
Mon, 18 Jan 2016 18:25:41 +0300 |
David Kiarie (4):
hw/i386: Introduce AMD IO MMU
hw/core: Add AMD IO MMU to machine properties
hw/i386: ACPI table for AMD IO MMU
hw/pci-host: Emulate AMD IO MMU
hw/core/machine.c | 17 +-
hw/i386/Makefile.objs | 1 +
hw/i386/acpi-build.c | 70 ++
hw/i386/amd_iommu.c | 1409 +++++++++++++++++++++++++++++++++++++++++
hw/i386/amd_iommu.h | 399 ++++++++++++
hw/pci-host/piix.c | 11 +
hw/pci-host/q35.c | 14 +-
include/hw/acpi/acpi-defs.h | 55 ++
include/hw/boards.h | 3 +-
include/hw/i386/intel_iommu.h | 1 +
include/hw/pci/pci.h | 2 +
qemu-options.hx | 6 +-
util/qemu-config.c | 4 +-
vl.c | 8 +
14 files changed, 1984 insertions(+), 16 deletions(-)
create mode 100644 hw/i386/amd_iommu.c
create mode 100644 hw/i386/amd_iommu.h
Hi all,
V4 of IO MMU patches.
Changes since V3
-Fixed Marcel's comments
-byte swapping in ACPI code fixed
As for IO MMU MMIO region:
This is the code that sets up the IO MMU base address in coreboot. It seems to
be reading something from the BUS config region which as per the comment should
have a value written by BIOS.
case CB_AmdSetMidPostConfig:
nbConfigPtr->pNbConfig->IoApicBaseAddress =
IO_APIC_ADDR;
#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
/* SBIOS must alloc 16K memory for IOMMU MMIO */
UINT32 MmcfgBarAddress; //using default
IOmmuBaseAddress
LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue |
0x1C,
AccessWidth32,
&MmcfgBarAddress,
nbConfigPtr);
MmcfgBarAddress &= ~0xf;
if (MmcfgBarAddress != 0) {
nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
}
nbConfigPtr->IommuBaseAddress = 0; //disable iommu
#endif
I have a feeling that this is getting overly and unnecessary complex - AMD have
their own BIOS which they, only know what it does and we have ours( which of
course, we know how it behaves).
If we choose a static address and assign that to IO MMU mmio we could
hypothetically have two problems.
-SeaBIOS allocating BAR from the same region.
-Someone selecting the region for other devices such as HPET.
The first problem can be solved as we know from what addresses seaBIOS allocats
BARs while as for the second they should know better. I have therefore selected
an unused IO region just next IOAPIC and HPET region and mapped 16K for IO MMU
mmio.
David.
--
2.1.4
- [Qemu-devel] [V4 0/4] AMD IO MMU,
David Kiarie <=
[Qemu-devel] [V4 1/4] hw/i386: Introduce AMD IO MMU, David Kiarie, 2016/01/18
[Qemu-devel] [V4 3/4] hw/i386: ACPI table for AMD IO MMU, David Kiarie, 2016/01/18
[Qemu-devel] [V4 4/4] hw/pci-host: Emulate AMD IO MMU, David Kiarie, 2016/01/18