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Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU
From: |
David kiarie |
Subject: |
Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU |
Date: |
Thu, 14 Jan 2016 19:29:40 +0300 |
On Thu, Jan 14, 2016 at 7:19 PM, Jan Kiszka <address@hidden> wrote:
> On 2016-01-14 17:09, David kiarie wrote:
>> On Thu, Jan 14, 2016 at 6:42 PM, Jan Kiszka <address@hidden> wrote:
>>> On 2016-01-14 16:39, Michael S. Tsirkin wrote:
>>>> On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote:
>>>>> On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin <address@hidden>
>>>>> wrote:
>>>>>> On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote:
>>>>>>> Add IVRS table for AMD IO MMU. Also reverve MMIO
>>>>>>
>>>>>> reserve?
>>>>>
>>>>> Yeah, typo.
>>>>>
>>>>>>
>>>>>>> region for IO MMU via ACPI
>>>>>>
>>>>>>
>>>>>> It does not look like you reserve anything.
>>>>>>
>>>>>> Pls add a link to hardware spec (in
>>>>>> the device implementation) so we can check
>>>>>> what does real hardware do.
>>>>>>
>>>>>> If this is it:
>>>>>> http://developer.amd.com/wordpress/media/2012/10/488821.pdf
>>>>>>
>>>>>> then the way that works seems to be by guest
>>>>>> programming the MMIO base.
>>>>>> We should do the same: patch seabios and EFI to do this.
>>>>>
>>>>> Yes, that's the spec.
>>>>>
>>>>> We thought this could be possible via ACPI (without patching BIOS ), no ?
>>>>
>>>> I don't see how. We should do it the way it happens on real hardware.
>>>>
>>>
>>> Doesn't Seabios retrieve certain ACPI fragments from QEMU via a
>>> pv-interface by now?
>>>
>>> Anyway, the question remains where this address comes from: The BIOS,
>>> which then writes it into some hw config register and reports it in
>>> addition via ACPI or the hardware (hard-wired).
>>
>> Will look at patching BIOS.
>
> Scanning through the spec again: As the address is not hard-wired but
> configured via registers in the extended capabilities of the
> corresponding PCI functions of an IOMMU (and also enabled that way!),
> it's up to the BIOS to allocate an appropriate address for a system.
Is there a way to modify IVRS/ACPI table from seabios because the same
address is supposed to be the IVRS table otherwise I'd have to
hard-code it :/
Anyway, will check.
>
> Jan
>
>
- Re: [Qemu-devel] [V3 2/4] hw/core: Add AMD IO MMU to machine properties, (continued)
- [Qemu-devel] [V3 1/4] hw/i386: Introduce AMD IO MMU, David Kiarie, 2016/01/14
- [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, David Kiarie, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, Michael S. Tsirkin, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, Michael S. Tsirkin, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, David kiarie, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, Michael S. Tsirkin, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, Jan Kiszka, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, David kiarie, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, Jan Kiszka, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU,
David kiarie <=
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, Kevin O'Connor, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, David kiarie, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, Kevin O'Connor, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, Valentine Sinitsyn, 2016/01/14
- Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU, David kiarie, 2016/01/15
[Qemu-devel] [V3 4/4] hw/pci-host: Emulate AMD IO MMU, David Kiarie, 2016/01/14