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[Qemu-devel] [PULL v2 35/59] pc: acpi: pci: move link devices into SSDT
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v2 35/59] pc: acpi: pci: move link devices into SSDT |
Date: |
Sat, 9 Jan 2016 23:41:03 +0200 |
From: Igor Mammedov <address@hidden>
Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/i386/acpi-build.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++
hw/i386/acpi-dsdt.dsl | 49 ++++----------------------------
2 files changed, 82 insertions(+), 44 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index c0f3c82..799efe5 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1429,9 +1429,49 @@ static void build_dbg_aml(Aml *table)
aml_append(table, scope);
}
+static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
+{
+ Aml *dev;
+ Aml *crs;
+ Aml *method;
+ uint32_t irqs[] = {5, 10, 11};
+
+ dev = aml_device("%s", name);
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_SHARED, irqs, ARRAY_SIZE(irqs)));
+ aml_append(dev, aml_name_decl("_PRS", crs));
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_call1("IQST", reg)));
+ aml_append(dev, method);
+
+ method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_or(reg, aml_int(0x80), reg));
+ aml_append(dev, method);
+
+ method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_call1("IQCR", reg)));
+ aml_append(dev, method);
+
+ method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
+ aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
+ aml_append(method, aml_store(aml_name("PRRI"), reg));
+ aml_append(dev, method);
+
+ return dev;
+ }
+
static void build_piix4_pci0_int(Aml *table)
{
+ Aml *dev;
+ Aml *crs;
Aml *field;
+ Aml *method;
+ uint32_t irqs;
Aml *sb_scope = aml_scope("_SB");
field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
@@ -1441,6 +1481,43 @@ static void build_piix4_pci0_int(Aml *table)
aml_append(field, aml_named_field("PRQ3", 8));
aml_append(sb_scope, field);
+ aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
+ aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
+ aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
+ aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
+
+ dev = aml_device("LNKS");
+ {
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(4)));
+
+ crs = aml_resource_template();
+ irqs = 9;
+ aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
+ AML_ACTIVE_HIGH, AML_SHARED,
+ &irqs, 1));
+ aml_append(dev, aml_name_decl("_PRS", crs));
+
+ /* The SCI cannot be disabled and is always attached to GSI 9,
+ * so these are no-ops. We only need this link to override the
+ * polarity to active high and match the content of the MADT.
+ */
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(0x0b)));
+ aml_append(dev, method);
+
+ method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
+ aml_append(dev, method);
+
+ method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_name("_PRS")));
+ aml_append(dev, method);
+
+ method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
+ aml_append(dev, method);
+ }
+ aml_append(sb_scope, dev);
+
aml_append(table, sb_scope);
}
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index c9b2725..b74cffd 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -152,49 +152,10 @@ DefinitionBlock (
Return (PRR0)
}
-#define define_link(link, uid, reg) \
- Device(link) { \
- Name(_HID, EISAID("PNP0C0F")) \
- Name(_UID, uid) \
- Name(_PRS, ResourceTemplate() { \
- Interrupt(, Level, ActiveHigh, Shared) { \
- 5, 10, 11 \
- } \
- }) \
- Method(_STA, 0, NotSerialized) { \
- Return (IQST(reg)) \
- } \
- Method(_DIS, 0, NotSerialized) { \
- Or(reg, 0x80, reg) \
- } \
- Method(_CRS, 0, NotSerialized) { \
- Return (IQCR(reg)) \
- } \
- Method(_SRS, 1, NotSerialized) { \
- CreateDWordField(Arg0, 0x05, PRRI) \
- Store(PRRI, reg) \
- } \
- }
-
- define_link(LNKA, 0, PRQ0)
- define_link(LNKB, 1, PRQ1)
- define_link(LNKC, 2, PRQ2)
- define_link(LNKD, 3, PRQ3)
-
- Device(LNKS) {
- Name(_HID, EISAID("PNP0C0F"))
- Name(_UID, 4)
- Name(_PRS, ResourceTemplate() {
- Interrupt(, Level, ActiveHigh, Shared) { 9 }
- })
-
- // The SCI cannot be disabled and is always attached to GSI 9,
- // so these are no-ops. We only need this link to override the
- // polarity to active high and match the content of the MADT.
- Method(_STA, 0, NotSerialized) { Return (0x0b) }
- Method(_DIS, 0, NotSerialized) { }
- Method(_CRS, 0, NotSerialized) { Return (_PRS) }
- Method(_SRS, 1, NotSerialized) { }
- }
+ External(LNKA, DeviceObj)
+ External(LNKB, DeviceObj)
+ External(LNKC, DeviceObj)
+ External(LNKD, DeviceObj)
+ External(LNKS, DeviceObj)
}
}
--
MST
- [Qemu-devel] [PULL v2 25/59] pc: acpi: move HPET from DSDT to SSDT, (continued)
- [Qemu-devel] [PULL v2 25/59] pc: acpi: move HPET from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 26/59] pc: acpi: move DBUG() from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 27/59] pc: acpi: move RTC device from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 28/59] pc: acpi: move KBD device from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 29/59] pc: acpi: move MOU device from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 30/59] pc: acpi: move FDC0 device from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 31/59] pc: acpi: move LPT device from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 32/59] pc: acpi: move COM devices from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 33/59] pc: acpi: move PIIX4 isa-bridge and pm devices into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 34/59] pc: acpi: move remaining GPE handlers into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 35/59] pc: acpi: pci: move link devices into SSDT,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v2 36/59] pc: acpi: piix4: move IQCR() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 37/59] pc: acpi: piix4: move IQST() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 38/59] pc: acpi: piix4: move PCI0._PRT() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 39/59] pc: acpi: piix4: move remaining PCI hotplug bits into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 40/59] pc: acpi: piix4: acpi move PCI0 device to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 41/59] pc: acpi: q35: move GSI links to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 42/59] pc: acpi: q35: move link devices to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 43/59] pc: acpi: q35: move IQCR() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 44/59] pc: acpi: q35: move IQST() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 46/59] pc: acpi: q35: move _PRT() into SSDT, Michael S. Tsirkin, 2016/01/09