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[Qemu-devel] [PATCH 06/25] target-sparc: Store %asi in TB flags
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 06/25] target-sparc: Store %asi in TB flags |
Date: |
Thu, 17 Dec 2015 15:11:52 -0800 |
Knowing the value of %asi at translation time means that we
can handle the common settings without a function call.
The steady state appears to be %asi == ASI_P, so that sparcv9
code can use offset forms of lda/sta. The %asi register gets
pushed and popped on entry to certain functions, but it rarely
takes on values other than ASI_P or ASI_AIUP. Therefore we're
unlikely to be expanding the set of TBs created.
Signed-off-by: Richard Henderson <address@hidden>
---
target-sparc/cpu.h | 2 ++
target-sparc/translate.c | 29 ++++++++++++++++++++---------
2 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index f3ae242..7f4d47f 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -691,6 +691,7 @@ trap_state* cpu_tsptr(CPUSPARCState* env);
#define TB_FLAG_MMU_MASK 7
#define TB_FLAG_FPU_ENABLED (1 << 4)
#define TB_FLAG_AM_ENABLED (1 << 5)
+#define TB_FLAG_ASI_SHIFT 24
static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
target_ulong *cs_base, int *pflags)
@@ -708,6 +709,7 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env,
target_ulong *pc,
&& (env->fprs & FPRS_FEF)) {
flags |= TB_FLAG_FPU_ENABLED;
}
+ flags |= env->asi << TB_FLAG_ASI_SHIFT;
#else
if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
flags |= TB_FLAG_FPU_ENABLED;
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 146060a..0e51ee4 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -54,7 +54,7 @@ static TCGv cpu_tbr;
#endif
static TCGv cpu_cond;
#ifdef TARGET_SPARC64
-static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
+static TCGv_i32 cpu_xcc, cpu_fprs;
static TCGv cpu_gsr;
static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
@@ -82,6 +82,9 @@ typedef struct DisasContext {
TCGv ttl[5];
int n_t32;
int n_ttl;
+#ifdef TARGET_SPARC64
+ int asi;
+#endif
} DisasContext;
typedef struct {
@@ -1966,19 +1969,19 @@ static inline void gen_ne_fop_QD(DisasContext *dc, int
rd, int rs,
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
static TCGv_i32 gen_get_asi(DisasContext *dc, int insn)
{
- TCGv_i32 r_asi = tcg_temp_new_i32();
+ int asi;
if (IS_IMM) {
#ifdef TARGET_SPARC64
- tcg_gen_mov_i32(r_asi, cpu_asi);
+ asi = dc->asi;
#else
gen_exception(dc, TT_ILL_INSN);
- tcg_gen_movi_i32(r_asi, 0);
+ asi = 0;
#endif
} else {
- tcg_gen_movi_i32(r_asi, GET_FIELD(insn, 19, 26));
+ asi = GET_FIELD(insn, 19, 26);
}
- return r_asi;
+ return tcg_const_i32(asi);
}
static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
@@ -2675,7 +2678,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x3: /* V9 rdasi */
- tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
+ tcg_gen_movi_tl(cpu_dst, dc->asi);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x4: /* V9 rdtick */
@@ -3589,7 +3592,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
case 0x3: /* V9 wrasi */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
- tcg_gen_trunc_tl_i32(cpu_asi, cpu_tmp0);
+ tcg_gen_st32_tl(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState, asi));
+ /* End TB to notice changed ASI. */
+ save_state(dc);
+ gen_op_next_insn();
+ tcg_gen_exit_tb(0);
+ dc->is_br = 1;
break;
case 0x6: /* V9 wrfprs */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
@@ -5167,6 +5176,9 @@ void gen_intermediate_code(CPUSPARCState * env,
TranslationBlock * tb)
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
dc->singlestep = (cs->singlestep_enabled || singlestep);
+#ifdef TARGET_SPARC64
+ dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
+#endif
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
@@ -5275,7 +5287,6 @@ void gen_intermediate_code_init(CPUSPARCState *env)
static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
#ifdef TARGET_SPARC64
{ &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
- { &cpu_asi, offsetof(CPUSPARCState, asi), "asi" },
{ &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
#else
{ &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
--
2.5.0
- [Qemu-devel] [PATCH 12/25] target-sparc: Add MMU_REAL_IDX, (continued)
- [Qemu-devel] [PATCH 12/25] target-sparc: Add MMU_REAL_IDX, Richard Henderson, 2015/12/17
- [Qemu-devel] [PATCH 17/25] target-sparc: Fix obvious error in ASI_M_BFILL, Richard Henderson, 2015/12/17
- [Qemu-devel] [PATCH 15/25] target-sparc: Introduce gen_check_align, Richard Henderson, 2015/12/17
- [Qemu-devel] [PATCH 14/25] target-sparc: Use QT0 to return results from ldda, Richard Henderson, 2015/12/17
- [Qemu-devel] [PATCH 19/25] target-sparc: Directly implement easy ldf/stf asis, Richard Henderson, 2015/12/17
- [Qemu-devel] [PATCH 20/25] target-sparc: Directly implement block and short ldf/stf asis, Richard Henderson, 2015/12/17
- [Qemu-devel] [PATCH 21/25] target-sparc: Remove helper_ldf_asi, helper_stf_asi, Richard Henderson, 2015/12/17
- [Qemu-devel] [PATCH 23/25] target-sparc: Use cpu_fsr in stfsr, Richard Henderson, 2015/12/17
- [Qemu-devel] [PATCH 24/25] target-sparc: Use cpu_loop_exit_restore from helper_check_ieee_exceptions, Richard Henderson, 2015/12/17
- [Qemu-devel] [PATCH 25/25] target-sparc: Elide duplicate updates to fprs, Richard Henderson, 2015/12/17
- [Qemu-devel] [PATCH 06/25] target-sparc: Store %asi in TB flags,
Richard Henderson <=
- [Qemu-devel] [PATCH 08/25] target-sparc: Pass TCGMemOp to gen_ld/st_asi, Richard Henderson, 2015/12/17
- Re: [Qemu-devel] [PATCH 00/25] target-sparc improvements, Richard Henderson, 2015/12/17
- Re: [Qemu-devel] [PATCH 00/25] target-sparc improvements, Mark Cave-Ayland, 2015/12/29