Re: [Qemu-devel] [Qemu-arm] [PATCH] target-arm: Priority masking with basepri on v7m

[Francois Baldassari]

Hi Peter,

I must be missing something obvious, but I do not have the original
email thread (I was not subscribed at the time) and thus am finding it
exceedingly difficult to apply the patches using git-am.

I would happily test the patches otherwise.

Any guidance here?

François

On Wed, Nov 18, 2015 at 9:56 AM, Peter Crosthwaite
<address@hidden> wrote:
> On Tue, Nov 17, 2015 at 1:52 PM, Francois Baldassari
> <address@hidden> wrote:
>> Thanks for the swift reply.
>>
>> Michael's changes look very good indeed. Thank you for pointing them out.
>>
>
> If you have tested them as working and fixing a problem for you, you
> should contribute a tested-by tag to the series.
>
> Regards,
> Peter
>
>> No need to consider this any further then.
>>
>> Cheers,
>>
>> François.
>>
>> On Tue, Nov 17, 2015 at 1:49 PM, Peter Maydell <address@hidden>
>> wrote:
>>>
>>> On 17 November 2015 at 21:40, François Baldassari
>>> <address@hidden> wrote:
>>> > On armv7m mcus, the BASEPRI register can be set to mask interrupts
>>> > above a certain priority.
>>> >
>>> > This changeset implements that functionality by way of the NVIC which
>>> > ultimately sets the interrupt mask in the GIC.
>>> >
>>> > Signed-off-by: François Baldassari <address@hidden>
>>>
>>> There are a lot of problems with our NVIC priority handling
>>> right now. You might like to take a look at the patch set that
>>> Michael Davidsaver sent out earlier this month:
>>> https://lists.nongnu.org/archive/html/qemu-devel/2015-11/msg01542.html
>>>
>>> That has some problems but I think it's probably the way we're
>>> going to go to fix up the NVIC.
>>>
>>> thanks
>>> -- PMM
>>
>>