Re: [Qemu-devel] [PATCH v2] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

[Maciej W. Rozycki]

On Mon, 19 Oct 2015, Leon Alrae wrote:

> >> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
> >> they require any particular mode for its FPU. This patch removes the checks
> >> that may break a program that uses these instructions.
> > 
> > That is correct. That said these instructions do require at least a
> > MIPS32R2 or a MIPS64R1 CPU. I guess we should add these checks now that
> > check_cop1x do not guard them anymore.
> 
> I suspect that this might too restrictive if we take into account also
> legacy processors. As far as I know these instructions were already
> present in MIPS IV implementations. I think it'll be safer if for the
> pre-MIPS32R2 and pre-MIPS64R1 CPUs we keep the check_cop1x. (actually
> I'm not certain if check_cop1x is correct, but at least we aren't
> relaxing the previous restrictions too much).

 These instructions are unrestricted in the MIPS IV ISA[1].  In the 
MIPS64r1 ISA the double-precision variants do require CP0.Status.FR=1[2].  
See also <https://gcc.gnu.org/ml/gcc-patches/2013-11/msg01695.html>.

References:

[1] "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, By 
    Charles Price, September, 1995, pp. B-83, B-86
    
<http://techpubs.sgi.com/library/manuals/2000/007-2597-001/pdf/007-2597-001.pdf>

[2] "MIPS Architecture For Programmers, Volume II: The MIPS64 Instruction 
    Set", MIPS Technologies, Inc., Document Number: MD00087, Revision 
    1.00, August 29, 2002, pp. 244, 258

  Maciej