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[Qemu-devel] [PATCH v5 13/14] target-arm: Route S2 MMU faults to EL2
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v5 13/14] target-arm: Route S2 MMU faults to EL2 |
Date: |
Mon, 26 Oct 2015 14:02:06 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/op_helper.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 36dac27..333078a 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -90,13 +90,19 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
is_write, int mmu_idx,
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
uint32_t syn, exc;
- bool same_el = (arm_current_el(env) != 0);
+ unsigned int target_el;
+ bool same_el;
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(cs, retaddr);
}
+ target_el = exception_target_el(env);
+ if (fi.stage2) {
+ target_el = 2;
+ }
+ same_el = arm_current_el(env) == target_el;
/* AArch64 syndrome does not have an LPAE bit */
syn = fsr & ~(1 << 9);
@@ -116,7 +122,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
is_write, int mmu_idx,
env->exception.vaddress = addr;
env->exception.fsr = fsr;
- raise_exception(env, exc, syn, exception_target_el(env));
+ raise_exception(env, exc, syn, target_el);
}
}
#endif
--
1.9.1
- [Qemu-devel] [PATCH v5 01/14] target-arm: Add HPFAR_EL2, (continued)
- [Qemu-devel] [PATCH v5 01/14] target-arm: Add HPFAR_EL2, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 03/14] target-arm: lpae: Move declaration of t0sz and t1sz, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 05/14] target-arm: lpae: Replace tsz with computed inputsize, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 04/14] target-arm: Add support for AArch32 S2 negative t0sz, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 06/14] target-arm: lpae: Rename granule_sz to stride, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 07/14] target-arm: Add computation of starting level for S2 PTW, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 08/14] target-arm: Add support for S2 page-table protection bits, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 09/14] target-arm: Avoid inline for get_phys_addr, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 10/14] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 11/14] target-arm: Add S2 translation to 64bit S1 PTWs, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 13/14] target-arm: Route S2 MMU faults to EL2,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v5 12/14] target-arm: Add S2 translation to 32bit S1 PTWs, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 14/14] target-arm: Add support for S1 + S2 MMU translations, Edgar E. Iglesias, 2015/10/26
- Re: [Qemu-devel] [PATCH v5 00/14] arm: Steps towards EL2 support round 5, Peter Maydell, 2015/10/27