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Re: [Qemu-devel] [kvm-unit-tests PATCHv4 3/3] arm: pmu: Add CPI checking
From: |
Andrew Jones |
Subject: |
Re: [Qemu-devel] [kvm-unit-tests PATCHv4 3/3] arm: pmu: Add CPI checking |
Date: |
Mon, 26 Oct 2015 13:25:33 +0100 |
User-agent: |
Mutt/1.5.23.1 (2014-03-12) |
On Mon, Oct 19, 2015 at 11:44:30AM -0400, Christopher Covington wrote:
> Hi Drew,
>
> I appreciate your feedback on these patches.
>
> On 10/18/2015 02:28 PM, Andrew Jones wrote:
>
> >> --- a/arm/pmu.c
> >> +++ b/arm/pmu.c
> >> @@ -37,6 +37,18 @@ static inline unsigned long get_pmccntr(void)
> >> asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (cycles));
> >> return cycles;
> >> }
> >> +
> >> +static inline void loop(int i, uint32_t pmcr)
> >> +{
> >> + uint32_t z = 0;
> >> +
> >> + asm volatile(
> >> + " mcr p15, 0, %[pmcr], c9, c12, 0\n"
> >> + " 1: subs %[i], %[i], #1\n"
> >> + " bgt 1b\n"
> >> + " mcr p15, 0, %[z], c9, c12, 0\n"
> >> + : [i] "+r" (i) : [pmcr] "r" (pmcr), [z] "r" (z) : "cc");
> >
> > Assembly is always ugly, but we can do a bit better formatting with tabs
> >
> > asm volatile(
> > " mcr p15, 0, %[pmcr], c9, c12, 0\n"
> > "1: subs %[i], %[i], #1\n"
> > " bgt 1b\n"
> > " mcr p15, 0, %[z], c9, c12, 0\n"
> > : [i] "+r" (i)
> > : [pmcr] "r" (pmcr), [z] "r" (z)
> > : "cc");
> >
> > Actually it can be even cleaner because you already created set_pmcr()
> >
> > set_pmcr(pmcr);
> >
> > asm volatile(
> > "1: subs %0, %0, #1\n"
> > " bgt 1b\n"
> > : "+r" (i) : : "cc");
> >
> > set_pmcr(0);
>
> Is there any way to ensure that the compiler won't for example put a `mov rd,
> #0` between the `bgt 1b` and the `mcr <pmcr>, rn`?
You're right. We need to keep the clearing in the asm here in order to
make sure don't add instructions in between.
>
> >> @@ -125,12 +147,79 @@ static bool check_cycles_increase(void)
> >> return true;
> >> }
> >>
> >> -int main(void)
> >> +/*
> >> + * Execute a known number of guest instructions. Only odd instruction
> >> counts
> >> + * greater than or equal to 3 are supported by the in-line assembly code.
> >> The
> >
> > Not all odd counts, right? But rather all multiples of 3? IIUC this is
> > because
> > the loop is two instructions (sub + branch), and then the clearing of the
> > pmcr
> > register counts as the 3rd?
>
> Clearing the PMCR doesn't happen as part of the loop, but as part of the loop
> exit or epilogue.
>
> total_instrs = iteration_count * loop_instrs + eipilogue_instrs
> total_instrs = iteration_count * 2 + 1
Ah yeah, that makes sense.
Thanks,
drew
>
> Thanks,
> Christopher Covington
>
> --
> Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
- [Qemu-devel] [kvm-unit-tests PATCHv3 1/3] arm: Add PMU test, (continued)
- [Qemu-devel] [kvm-unit-tests PATCHv4] ARM PMU tests, Christopher Covington, 2015/10/15
- [Qemu-devel] [kvm-unit-tests PATCHv4 1/3] arm: Add PMU test, Christopher Covington, 2015/10/15
- Re: [Qemu-devel] [kvm-unit-tests PATCHv4 1/3] arm: Add PMU test, Andrew Jones, 2015/10/18
- [Qemu-devel] [kvm-unit-tests PATCHv4 2/3] arm: pmu: Check cycle count increases, Christopher Covington, 2015/10/15
- Re: [Qemu-devel] [kvm-unit-tests PATCHv4 2/3] arm: pmu: Check cycle count increases, Andrew Jones, 2015/10/18
- [Qemu-devel] [kvm-unit-tests PATCHv4 3/3] arm: pmu: Add CPI checking, Christopher Covington, 2015/10/15
- Re: [Qemu-devel] [kvm-unit-tests PATCHv4 3/3] arm: pmu: Add CPI checking, Andrew Jones, 2015/10/18
- Re: [Qemu-devel] [kvm-unit-tests PATCHv4 3/3] arm: pmu: Add CPI checking, Christopher Covington, 2015/10/19
- Re: [Qemu-devel] [kvm-unit-tests PATCHv4 3/3] arm: pmu: Add CPI checking,
Andrew Jones <=
- Re: [Qemu-devel] [kvm-unit-tests PATCHv4] ARM PMU tests, Andrew Jones, 2015/10/18
- [Qemu-devel] [kvm-unit-tests PATCHv5] ARM PMU tests, Christopher Covington, 2015/10/26
- [Qemu-devel] [kvm-unit-tests PATCHv5 1/3] arm: Add PMU test, Christopher Covington, 2015/10/26
- [Qemu-devel] [kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases, Christopher Covington, 2015/10/26
- Re: [Qemu-devel] [kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases, Andrew Jones, 2015/10/26
- Re: [Qemu-devel] [kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases, Christopher Covington, 2015/10/26
- Re: [Qemu-devel] [kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases, Andrew Jones, 2015/10/26
- [Qemu-devel] [kvm-unit-tests PATCHv5 3/3] arm: pmu: Add CPI checking, Christopher Covington, 2015/10/26
- Re: [Qemu-devel] [kvm-unit-tests PATCHv5 3/3] arm: pmu: Add CPI checking, Andrew Jones, 2015/10/26
- [Qemu-devel] [kvm-unit-tests PATCHv6] ARM PMU tests, Christopher Covington, 2015/10/28