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Re: [Qemu-devel] [PATCH v4 12/13] target-arm: Route S2 MMU faults to EL2
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v4 12/13] target-arm: Route S2 MMU faults to EL2 |
Date: |
Fri, 23 Oct 2015 17:56:53 +0100 |
On 14 October 2015 at 23:55, Edgar E. Iglesias <address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>
> ---
> target-arm/op_helper.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index d4715f4..2ccd1c9 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -90,13 +90,19 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
> is_write, int mmu_idx,
> ARMCPU *cpu = ARM_CPU(cs);
> CPUARMState *env = &cpu->env;
> uint32_t syn, exc;
> - bool same_el = (arm_current_el(env) != 0);
> + unsigned int target_el;
> + bool same_el;
>
> if (retaddr) {
> /* now we have a real cpu fault */
> cpu_restore_state(cs, retaddr);
> }
>
> + target_el = exception_target_el(env);
> + if (fi.stage2) {
> + target_el = 2;
> + }
> + same_el = arm_current_el(env) == target_el;
> /* AArch64 syndrome does not have an LPAE bit */
> syn = fsr & ~(1 << 9);
>
> @@ -116,7 +122,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
> is_write, int mmu_idx,
>
> env->exception.vaddress = addr;
> env->exception.fsr = fsr;
> - raise_exception(env, exc, syn, exception_target_el(env));
> + raise_exception(env, exc, syn, target_el);
> }
> }
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- [Qemu-devel] [PATCH v4 01/13] target-arm: Add HPFAR_EL2, (continued)
- [Qemu-devel] [PATCH v4 04/13] target-arm: lpae: Replace tsz with computed inputsize, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 11/13] target-arm: Add S2 translation to 32bit S1 PTWs, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 12/13] target-arm: Route S2 MMU faults to EL2, Edgar E. Iglesias, 2015/10/14
- Re: [Qemu-devel] [PATCH v4 12/13] target-arm: Route S2 MMU faults to EL2,
Peter Maydell <=
- [Qemu-devel] [PATCH v4 09/13] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 10/13] target-arm: Add S2 translation to 64bit S1 PTWs, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 07/13] target-arm: Add support for S2 page-table protection bits, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 08/13] target-arm: Avoid inline for get_phys_addr, Edgar E. Iglesias, 2015/10/14
- [Qemu-devel] [PATCH v4 13/13] target-arm: Add support for S1 + S2 MMU translations, Edgar E. Iglesias, 2015/10/14