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[Qemu-devel] [PULL 01/13] target-i386: allow any alignment for SMBASE
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 01/13] target-i386: allow any alignment for SMBASE |
Date: |
Fri, 23 Oct 2015 13:33:00 -0200 |
From: Paolo Bonzini <address@hidden>
Processors up to the Pentium (says Bochs---I do not have old enough
manuals) require a 32KiB alignment for the SMBASE, but newer processors
do not need that, and Tiano Core will use non-aligned SMBASE values.
Reported-by: Michael D Kinney <address@hidden>
Cc: Laszlo Ersek <address@hidden>
Cc: Jordan Justen <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
target-i386/smm_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 02e24b9..c272a98 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -266,7 +266,7 @@ void helper_rsm(CPUX86State *env)
val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) {
- env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00) & ~0x7fff;
+ env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);
}
#else
cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
@@ -319,7 +319,7 @@ void helper_rsm(CPUX86State *env)
val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) {
- env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8) & ~0x7fff;
+ env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);
}
#endif
if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {
--
2.1.0
- [Qemu-devel] [PULL 00/13] X86 queue, 2015-10-23, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 02/13] target-i386: Disable cache info passthrough by default, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 01/13] target-i386: allow any alignment for SMBASE,
Eduardo Habkost <=
- [Qemu-devel] [PULL 03/13] target-i386: Introduce cpu_x86_update_dr7, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 04/13] target-i386: Re-introduce optimal breakpoint removal, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 05/13] target-i386: Ensure bit 10 on DR7 is never cleared, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 07/13] target-i386: Optimize setting dr[0-3], Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 06/13] target-i386: Move hw_*breakpoint_* functions, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 08/13] target-i386: Handle I/O breakpoints, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 10/13] target-i386: Ensure always-1 bits on DR6 can't be cleared, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 09/13] target-i386: Check CR4[DE] for processing DR4/DR5, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 11/13] target-i386: Add DE to TCG_FEATURES, Eduardo Habkost, 2015/10/23
- [Qemu-devel] [PULL 12/13] target-i386: Use 1UL for bit shift, Eduardo Habkost, 2015/10/23