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[Qemu-devel] [PATCH v3 2/6] disas/mips: Add R6 jr/jr.hb to disassembler
From: |
James Hogan |
Subject: |
[Qemu-devel] [PATCH v3 2/6] disas/mips: Add R6 jr/jr.hb to disassembler |
Date: |
Fri, 2 Oct 2015 13:24:13 +0100 |
MIPS r6 encodes jr as jalr zero, and jr.hb as jalr.hb zero, so add these
encodings to the MIPS disassembly table.
Signed-off-by: James Hogan <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Cc: Aurelien Jarno <address@hidden>
---
Changes in v3:
- Whoops. Fix jr.hb r6 encoding (Leon)
---
disas/mips.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index 01336a83852d..bf0bbaf86a3c 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -2420,9 +2420,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"hibernate","", 0x42000023, 0xffffffff, 0,
0, V1 },
{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,
0, I33 },
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0,
I1 },
+{"jr", "s", 0x00000009, 0xfc1fffff, UBD|RD_s, 0,
I32R6 }, /* jalr */
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
the same hazard barrier effect. */
{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0,
I32 },
+{"jr.hb", "s", 0x00000409, 0xfc1fffff, UBD|RD_s, 0,
I32R6 }, /* jalr.hb */
{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0,
I1 }, /* jr */
/* SVR4 PIC code requires special handling for j, so it must be a
macro. */
--
2.4.9
Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ, Aurelien Jarno, 2015/10/09
[Qemu-devel] [PATCH v3 3/6] tcg/mips: Add use_mips32r6_instructions definition, James Hogan, 2015/10/08
[Qemu-devel] [PATCH v3 4/6] tcg/mips: Support r6 JR encoding, James Hogan, 2015/10/08
[Qemu-devel] [PATCH v3 2/6] disas/mips: Add R6 jr/jr.hb to disassembler,
James Hogan <=
[Qemu-devel] [PATCH v3 5/6] tcg/mips: Support r6 multiply/divide encodings, James Hogan, 2015/10/08