Re: [Qemu-devel] [PATCH] target-tilegx: Check zero dest register for ld instructions

[Chen Gang]

On 10/1/15 10:29, Richard Henderson wrote:
> On 09/28/2015 11:51 PM, address@hidden wrote:
>> From: Chen Gang <address@hidden>
>>
>> At present, qemu x86_64 host backend can not remove the related dummy
>> instructions. Even the worse, sometimes, it will generate the incorrect
>> instructions which will cause segment fault for prefetch_l3 instruction.
>>
>> Signed-off-by: Chen Gang <address@hidden>
>> ---
>> target-tilegx/translate.c | 10 +++++++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
>> index 86da6b5..7232361 100644
>> --- a/target-tilegx/translate.c
>> +++ b/target-tilegx/translate.c
>> @@ -620,7 +620,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned 
>> opext,
>> memop = MO_TEQ;
>> mnemonic = "ld";
>> do_load:
>> - tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
>> + if (dest != TILEGX_R_ZERO) {
>> + tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
>> + }
>
> This isn't right. Not all load instructions are nofault prefetches.
>

OK, thanks.

--
Chen Gang (陈刚)

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