Re: [Qemu-devel] [PATCH RFC 0/8] arm: Steps towards EL2 support round 5

[Peter Maydell]

On 19 September 2015 at 07:15, Edgar E. Iglesias
<address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Hi,
>
> Another round of patches towards EL2 support. This one adds partial
> support for 2-stage MMU for AArch64. I've marked it RFC because I
> expect a few iterations. Once we can settle on the approach I'll
> add the AArch32 support (changes for arm_ldl_ptw etc). I've probably
> missed alot of details aswell.
>
> Some of the details of error reporting are intentionally missing, I
> was thinking to add those incrementally as they get quite involved
> (e.g the register target and memory access size).
>
> Some of the patches at the start of the series might be good already,
> please pick them up if you agree Peter!
>
> Comments welcome!
>
> Best regards,
> Edgar
>
> Edgar E. Iglesias (8):
>   target-arm: Add HPFAR_EL2
>   target-arm: Add computation of starting level for S2 PTW
>   target-arm: Add support for S2 page-table protection bits
>   target-arm: Avoid inline for get_phys_addr
>   target-arm: Add ARMMMUFaultInfo
>   target-arm: Add S2 translation support for S1 PTW
>   target-arm: Route S2 MMU faults to EL2
>   target-arm: Add support for S1 + S2 MMU translations

I've reviewed the easy patches at the start of this series.
IIRC you said you'd found some issues with it anyway and were
planning to do a v2 in a bit, so I'll wait for that rather
than trying to tackle the last few patches now.

thanks
-- PMM