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Re: [Qemu-devel] [PATCH V6 2/2] sdhci: Split sdhci.h for public and inte


From: Alistair Francis
Subject: Re: [Qemu-devel] [PATCH V6 2/2] sdhci: Split sdhci.h for public and internal device usage
Date: Tue, 22 Sep 2015 16:38:21 -0700

On Mon, Sep 21, 2015 at 11:28 PM, Sai Pavan Boddu
<address@hidden> wrote:
> Split sdhci.h into Pubilc version (i.e include/hw/sd/sdhci.h) and
> Internal version (i.e hw/sd/sdhci-interna.h) based on register
> declarations and object declaration.
>
> Signed-off-by: Sai Pavan Boddu <address@hidden>

Reviewed-by: Alistair Francis <address@hidden>

Thanks,

Alistair

> ---
> Changes for V6:
>     Fix commit message.
> Chages for V5:
>     Rename pubilc header version as sdhci.h and internal version to
> sdhci-internal.h
> Changes for V4:
>     Remain the name of internal version of sdchi.h as same. And change
>     Re-Adding qemu-common.h header.
> the one which is in includes/ to sdhci-common.h
> Changes for V2:
>     Create new area in includes for sd. And move sdhci.h to same.
> Changes for V3:
>     Split the headers to public and common.
> ---
>  hw/sd/{sdhci.h => sdhci-internal.h} | 67 +--------------------------
>  hw/sd/sdhci.c                       |  3 +-
>  include/hw/sd/sdhci.h               | 92 
> +++++++++++++++++++++++++++++++++++++
>  3 files changed, 95 insertions(+), 67 deletions(-)
>  rename hw/sd/{sdhci.h => sdhci-internal.h} (75%)
>  create mode 100644 include/hw/sd/sdhci.h
>
> diff --git a/hw/sd/sdhci.h b/hw/sd/sdhci-internal.h
> similarity index 75%
> rename from hw/sd/sdhci.h
> rename to hw/sd/sdhci-internal.h
> index a45593f..c40ae2b 100644
> --- a/hw/sd/sdhci.h
> +++ b/hw/sd/sdhci-internal.h
> @@ -21,14 +21,10 @@
>   * You should have received a copy of the GNU General Public License along
>   * with this program; if not, see <http://www.gnu.org/licenses/>.
>   */
> -
>  #ifndef SDHCI_H
>  #define SDHCI_H
>
> -#include "qemu-common.h"
> -#include "hw/pci/pci.h"
> -#include "hw/sysbus.h"
> -#include "hw/sd/sd.h"
> +#include "hw/sd/sdhci.h"
>
>  /* R/W SDMA System Address register 0x0 */
>  #define SDHC_SYSAD                     0x00
> @@ -231,65 +227,6 @@ enum {
>      sdhc_gap_write  = 2   /* SDHC stopped at block gap during write 
> operation */
>  };
>
> -/* SD/MMC host controller state */
> -typedef struct SDHCIState {
> -    union {
> -        PCIDevice pcidev;
> -        SysBusDevice busdev;
> -    };
> -    SDState *card;
> -    MemoryRegion iomem;
> -
> -    QEMUTimer *insert_timer;       /* timer for 'changing' sd card. */
> -    QEMUTimer *transfer_timer;
> -    qemu_irq eject_cb;
> -    qemu_irq ro_cb;
> -    qemu_irq irq;
> -
> -    uint32_t sdmasysad;    /* SDMA System Address register */
> -    uint16_t blksize;      /* Host DMA Buff Boundary and Transfer BlkSize 
> Reg */
> -    uint16_t blkcnt;       /* Blocks count for current transfer */
> -    uint32_t argument;     /* Command Argument Register */
> -    uint16_t trnmod;       /* Transfer Mode Setting Register */
> -    uint16_t cmdreg;       /* Command Register */
> -    uint32_t rspreg[4];    /* Response Registers 0-3 */
> -    uint32_t prnsts;       /* Present State Register */
> -    uint8_t  hostctl;      /* Host Control Register */
> -    uint8_t  pwrcon;       /* Power control Register */
> -    uint8_t  blkgap;       /* Block Gap Control Register */
> -    uint8_t  wakcon;       /* WakeUp Control Register */
> -    uint16_t clkcon;       /* Clock control Register */
> -    uint8_t  timeoutcon;   /* Timeout Control Register */
> -    uint8_t  admaerr;      /* ADMA Error Status Register */
> -    uint16_t norintsts;    /* Normal Interrupt Status Register */
> -    uint16_t errintsts;    /* Error Interrupt Status Register */
> -    uint16_t norintstsen;  /* Normal Interrupt Status Enable Register */
> -    uint16_t errintstsen;  /* Error Interrupt Status Enable Register */
> -    uint16_t norintsigen;  /* Normal Interrupt Signal Enable Register */
> -    uint16_t errintsigen;  /* Error Interrupt Signal Enable Register */
> -    uint16_t acmd12errsts; /* Auto CMD12 error status register */
> -    uint64_t admasysaddr;  /* ADMA System Address Register */
> -
> -    uint32_t capareg;      /* Capabilities Register */
> -    uint32_t maxcurr;      /* Maximum Current Capabilities Register */
> -    uint8_t  *fifo_buffer; /* SD host i/o FIFO buffer */
> -    uint32_t buf_maxsz;
> -    uint16_t data_count;   /* current element in FIFO buffer */
> -    uint8_t  stopped_state;/* Current SDHC state */
> -    /* Buffer Data Port Register - virtual access point to R and W buffers */
> -    /* Software Reset Register - always reads as 0 */
> -    /* Force Event Auto CMD12 Error Interrupt Reg - write only */
> -    /* Force Event Error Interrupt Register- write only */
> -    /* RO Host Controller Version Register always reads as 0x2401 */
> -} SDHCIState;
> -
>  extern const VMStateDescription sdhci_vmstate;
>
> -#define TYPE_PCI_SDHCI "sdhci-pci"
> -#define PCI_SDHCI(obj) OBJECT_CHECK(SDHCIState, (obj), TYPE_PCI_SDHCI)
> -
> -#define TYPE_SYSBUS_SDHCI "generic-sdhci"
> -#define SYSBUS_SDHCI(obj)                               \
> -     OBJECT_CHECK(SDHCIState, (obj), TYPE_SYSBUS_SDHCI)
> -
> -#endif /* SDHCI_H */
> +#endif
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index e63367b..34018fd 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -28,8 +28,7 @@
>  #include "sysemu/dma.h"
>  #include "qemu/timer.h"
>  #include "qemu/bitops.h"
> -
> -#include "sdhci.h"
> +#include "sdhci-internal.h"
>
>  /* host controller debug messages */
>  #ifndef SDHC_DEBUG
> diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
> new file mode 100644
> index 0000000..62c300b
> --- /dev/null
> +++ b/include/hw/sd/sdhci.h
> @@ -0,0 +1,92 @@
> +/*
> + * SD Association Host Standard Specification v2.0 controller emulation
> + *
> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
> + * Mitsyanko Igor <address@hidden>
> + * Peter A.G. Crosthwaite <address@hidden>
> + *
> + * Based on MMC controller for Samsung S5PC1xx-based board emulation
> + * by Alexey Merkulov and Vladimir Monakhov.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
> + * See the GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU _General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef SDHCI_COMMON_H
> +#define SDHCI_COMMON_H
> +
> +#include "qemu-common.h"
> +#include "hw/pci/pci.h"
> +#include "hw/sysbus.h"
> +#include "hw/sd/sd.h"
> +
> +/* SD/MMC host controller state */
> +typedef struct SDHCIState {
> +    union {
> +        PCIDevice pcidev;
> +        SysBusDevice busdev;
> +    };
> +    SDState *card;
> +    MemoryRegion iomem;
> +
> +    QEMUTimer *insert_timer;       /* timer for 'changing' sd card. */
> +    QEMUTimer *transfer_timer;
> +    qemu_irq eject_cb;
> +    qemu_irq ro_cb;
> +    qemu_irq irq;
> +
> +    uint32_t sdmasysad;    /* SDMA System Address register */
> +    uint16_t blksize;      /* Host DMA Buff Boundary and Transfer BlkSize 
> Reg */
> +    uint16_t blkcnt;       /* Blocks count for current transfer */
> +    uint32_t argument;     /* Command Argument Register */
> +    uint16_t trnmod;       /* Transfer Mode Setting Register */
> +    uint16_t cmdreg;       /* Command Register */
> +    uint32_t rspreg[4];    /* Response Registers 0-3 */
> +    uint32_t prnsts;       /* Present State Register */
> +    uint8_t  hostctl;      /* Host Control Register */
> +    uint8_t  pwrcon;       /* Power control Register */
> +    uint8_t  blkgap;       /* Block Gap Control Register */
> +    uint8_t  wakcon;       /* WakeUp Control Register */
> +    uint16_t clkcon;       /* Clock control Register */
> +    uint8_t  timeoutcon;   /* Timeout Control Register */
> +    uint8_t  admaerr;      /* ADMA Error Status Register */
> +    uint16_t norintsts;    /* Normal Interrupt Status Register */
> +    uint16_t errintsts;    /* Error Interrupt Status Register */
> +    uint16_t norintstsen;  /* Normal Interrupt Status Enable Register */
> +    uint16_t errintstsen;  /* Error Interrupt Status Enable Register */
> +    uint16_t norintsigen;  /* Normal Interrupt Signal Enable Register */
> +    uint16_t errintsigen;  /* Error Interrupt Signal Enable Register */
> +    uint16_t acmd12errsts; /* Auto CMD12 error status register */
> +    uint64_t admasysaddr;  /* ADMA System Address Register */
> +
> +    uint32_t capareg;      /* Capabilities Register */
> +    uint32_t maxcurr;      /* Maximum Current Capabilities Register */
> +    uint8_t  *fifo_buffer; /* SD host i/o FIFO buffer */
> +    uint32_t buf_maxsz;
> +    uint16_t data_count;   /* current element in FIFO buffer */
> +    uint8_t  stopped_state;/* Current SDHC state */
> +    /* Buffer Data Port Register - virtual access point to R and W buffers */
> +    /* Software Reset Register - always reads as 0 */
> +    /* Force Event Auto CMD12 Error Interrupt Reg - write only */
> +    /* Force Event Error Interrupt Register- write only */
> +    /* RO Host Controller Version Register always reads as 0x2401 */
> +} SDHCIState;
> +
> +#define TYPE_PCI_SDHCI "sdhci-pci"
> +#define PCI_SDHCI(obj) OBJECT_CHECK(SDHCIState, (obj), TYPE_PCI_SDHCI)
> +
> +#define TYPE_SYSBUS_SDHCI "generic-sdhci"
> +#define SYSBUS_SDHCI(obj)                               \
> +     OBJECT_CHECK(SDHCIState, (obj), TYPE_SYSBUS_SDHCI)
> +
> +#endif /* SDHCI_H */
> --
> 2.1.4
>
>



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