[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v3 08/25] target-mips: Add delayed branch state to i
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 08/25] target-mips: Add delayed branch state to insn_start |
Date: |
Tue, 22 Sep 2015 13:24:50 -0700 |
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-mips/cpu.h | 1 +
target-mips/translate.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index ed7d86d..fd23832 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -132,6 +132,7 @@ struct CPUMIPSFPUContext {
};
#define NB_MMU_MODES 3
+#define TARGET_INSN_START_EXTRA_WORDS 2
typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
struct CPUMIPSMVPContext {
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 57e826d..30d7d46 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19562,6 +19562,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu,
TranslationBlock *tb,
ctx.CP0_Config1 = env->CP0_Config1;
ctx.tb = tb;
ctx.bstate = BS_NONE;
+ ctx.btarget = 0;
ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
@@ -19603,7 +19604,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu,
TranslationBlock *tb,
tcg_ctx.gen_opc_instr_start[lj] = 1;
tcg_ctx.gen_opc_icount[lj] = num_insns;
}
- tcg_gen_insn_start(ctx.pc);
+ tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
num_insns++;
if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
--
2.4.3
- [Qemu-devel] [PATCH v3 03/25] target-*: Increment num_insns immediately after tcg_gen_insn_start, (continued)
- [Qemu-devel] [PATCH v3 03/25] target-*: Increment num_insns immediately after tcg_gen_insn_start, Richard Henderson, 2015/09/22
- [Qemu-devel] [PATCH v3 06/25] target-arm: Add condexec state to insn_start, Richard Henderson, 2015/09/22
- [Qemu-devel] [PATCH v3 05/25] tcg: Allow extra data to be attached to insn_start, Richard Henderson, 2015/09/22
- [Qemu-devel] [PATCH v3 04/25] target-*: Introduce and use cpu_breakpoint_test, Richard Henderson, 2015/09/22
- [Qemu-devel] [PATCH v3 09/25] target-s390x: Add cc_op state to insn_start, Richard Henderson, 2015/09/22
- [Qemu-devel] [PATCH v3 07/25] target-i386: Add cc_op state to insn_start, Richard Henderson, 2015/09/22
- [Qemu-devel] [PATCH v3 08/25] target-mips: Add delayed branch state to insn_start,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 10/25] target-sh4: Add flags state to insn_start, Richard Henderson, 2015/09/22
- [Qemu-devel] [PATCH v3 12/25] target-sparc: Tidy gen_branch_a interface, Richard Henderson, 2015/09/22
- [Qemu-devel] [PATCH v3 11/25] target-cris: Mirror gen_opc_pc into insn_start, Richard Henderson, 2015/09/22
- [Qemu-devel] [PATCH v3 13/25] target-sparc: Split out gen_branch_n, Richard Henderson, 2015/09/22
- [Qemu-devel] [PATCH v3 16/25] tcg: Merge cpu_gen_code into tb_gen_code, Richard Henderson, 2015/09/22
- [Qemu-devel] [PATCH v3 20/25] tcg: Save insn data and use it in cpu_restore_state_from_tb, Richard Henderson, 2015/09/22