Re: [Qemu-devel] [PATCH RFC 0/8] arm: Steps towards EL2 support round 5

[Edgar E. Iglesias]

On Sat, Sep 19, 2015 at 07:15:19AM -0700, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <address@hidden>
> 
> Hi,
> 
> Another round of patches towards EL2 support. This one adds partial
> support for 2-stage MMU for AArch64. I've marked it RFC because I
> expect a few iterations. Once we can settle on the approach I'll
> add the AArch32 support (changes for arm_ldl_ptw etc). I've probably
> missed alot of details aswell.

Another note, the mem attributes handling is also not considered yet.
For example the user attribute when doing S2 and so one.
It wasn't super clear to me howto reorg the code and how the specs
works here so I will have to revisit that aswell. If you have comments
on how it should work those are greatly appreciated :-)

Cheers,
Edgar



> 
> Some of the details of error reporting are intentionally missing, I
> was thinking to add those incrementally as they get quite involved
> (e.g the register target and memory access size).
> 
> Some of the patches at the start of the series might be good already,
> please pick them up if you agree Peter!
> 
> Comments welcome!
> 
> Best regards,
> Edgar
> 
> Edgar E. Iglesias (8):
>   target-arm: Add HPFAR_EL2
>   target-arm: Add computation of starting level for S2 PTW
>   target-arm: Add support for S2 page-table protection bits
>   target-arm: Avoid inline for get_phys_addr
>   target-arm: Add ARMMMUFaultInfo
>   target-arm: Add S2 translation support for S1 PTW
>   target-arm: Route S2 MMU faults to EL2
>   target-arm: Add support for S1 + S2 MMU translations
> 
>  target-arm/cpu.h       |   1 +
>  target-arm/helper.c    | 211 
> ++++++++++++++++++++++++++++++++++++++++---------
>  target-arm/internals.h |  10 ++-
>  target-arm/op_helper.c |  17 ++--
>  4 files changed, 197 insertions(+), 42 deletions(-)
> 
> -- 
> 1.9.1
>