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[Qemu-devel] [PATCH RFC 8/8] target-arm: Add support for S1 + S2 MMU tra
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH RFC 8/8] target-arm: Add support for S1 + S2 MMU translations |
Date: |
Sat, 19 Sep 2015 07:15:27 -0700 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper.c | 44 +++++++++++++++++++++++++++++++++++++-------
1 file changed, 37 insertions(+), 7 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index eac1a25..5710dfc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -7023,14 +7023,44 @@ static bool get_phys_addr(CPUARMState *env,
target_ulong address,
ARMMMUFaultInfo *fi)
{
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
- /* TODO: when we support EL2 we should here call ourselves recursively
- * to do the stage 1 and then stage 2 translations. The arm_ld*_ptw
- * functions will also need changing to perform ARMMMUIdx_S2NS loads
- * rather than direct physical memory loads when appropriate.
- * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
+ /* Call ourselves recursively to do the stage 1 and then stage 2
+ * translations.
*/
- assert(!arm_feature(env, ARM_FEATURE_EL2));
- mmu_idx += ARMMMUIdx_S1NSE0;
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
+ hwaddr ipa;
+ int s2_prot;
+ int ret;
+
+ ret = get_phys_addr(env, address, access_type,
+ mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
+ prot, page_size, fsr, fi);
+
+ /* If S1 fails or S2 is disabled, return early. */
+ if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
+ if (ret && fi->stage2) {
+ /* This is a S2 error while doing S1 PTW. */
+ env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
+ }
+ *phys_ptr = ipa;
+ return ret;
+ }
+
+ /* S1 is done. Now do S2 translation. */
+ ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
+ phys_ptr, attrs, &s2_prot,
+ page_size, fsr, fi);
+ if (ret) {
+ env->cp15.hpfar_el2 = extract64(ipa, 12, 47) << 4;
+ }
+ /* Combine the S1 and S2 perms. */
+ *prot &= s2_prot;
+ return ret;
+ } else {
+ /*
+ * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
+ */
+ mmu_idx += ARMMMUIdx_S1NSE0;
+ }
}
/* The page table entries may downgrade secure to non-secure, but
--
1.9.1
- [Qemu-devel] [PATCH RFC 2/8] target-arm: Add computation of starting level for S2 PTW, (continued)
- [Qemu-devel] [PATCH RFC 2/8] target-arm: Add computation of starting level for S2 PTW, Edgar E. Iglesias, 2015/09/19
- [Qemu-devel] [PATCH RFC 3/8] target-arm: Add support for S2 page-table protection bits, Edgar E. Iglesias, 2015/09/19
- [Qemu-devel] [PATCH RFC 4/8] target-arm: Avoid inline for get_phys_addr, Edgar E. Iglesias, 2015/09/19
- [Qemu-devel] [PATCH RFC 5/8] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/09/19
- [Qemu-devel] [PATCH RFC 6/8] target-arm: Add S2 translation support for S1 PTW, Edgar E. Iglesias, 2015/09/19
- [Qemu-devel] [PATCH RFC 7/8] target-arm: Route S2 MMU faults to EL2, Edgar E. Iglesias, 2015/09/19
- [Qemu-devel] [PATCH RFC 8/8] target-arm: Add support for S1 + S2 MMU translations,
Edgar E. Iglesias <=
- Re: [Qemu-devel] [PATCH RFC 0/8] arm: Steps towards EL2 support round 5, Edgar E. Iglesias, 2015/09/19
- Re: [Qemu-devel] [PATCH RFC 0/8] arm: Steps towards EL2 support round 5, Peter Maydell, 2015/09/23