[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 00/22] Do away with TB retranslation
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 00/22] Do away with TB retranslation |
Date: |
Thu, 17 Sep 2015 21:55:07 -0700 |
Version 2, updated based on comments. Notable changes:
(1) Move breakpoint recognition after insn_start. Now we really
do never have zero insns per TB. Assertions added.
(2) Comments added.
(3) Minor tweeks to the encoding, reflected in the comments.
I examined a handfull of test cases, and compiled some sizes:
AVG DATA/TB CODE+DATA EXPAND
aarch64-test 15.6 17.7
arm-test 15.9 18.6
sparc-test 18.9 13.6
ppc-test 11.4 14.8
mb-test 12.3 13.5
coldfire-test 10.8 25.0
s390 moonbuggy 16.0 17.7
alpha 12.6 12.7
mips64 31.6 14.8
ppc64 13.5 16.6
Not surprising that mips is larger, since it requests 3 words
of ancilliary data, more than anyone else. With less than 20
bytes per TB on average, I'm not sure that anything else is
required wrt compression.
r~
Richard Henderson (22):
tcg: Rename debug_insn_start to insn_start
target-*: Unconditionally emit tcg_gen_insn_start
target-*: Increment num_insns immediately after tcg_gen_insn_start
target-*: Introduce and use cpu_breakpoint_test
tcg: Allow extra data to be attached to insn_start
target-arm: Add condexec state to insn_start
target-i386: Add cc_op state to insn_start
target-mips: Add delayed branch state to insn_start
target-s390x: Add cc_op state to insn_start
target-sh4: Add flags state to insn_start
target-cris: Mirror gen_opc_pc into insn_start
target-sparc: Tidy gen_branch_a interface
target-sparc: Split out gen_branch_n
target-sparc: Remove gen_opc_jump_pc
target-sparc: Add npc state to insn_start
tcg: Merge cpu_gen_code into tb_gen_code
target-*: Drop cpu_gen_code define
tcg: Add TCG_MAX_INSNS
tcg: Pass data argument to restore_state_to_opc
tcg: Save insn data and use it in cpu_restore_state_from_tb
tcg: Remove gen_intermediate_code_pc
tcg: Remove tcg_gen_code_search_pc
include/exec/exec-all.h | 6 +-
include/qom/cpu.h | 16 +++
target-alpha/cpu.h | 1 -
target-alpha/translate.c | 70 +++---------
target-arm/cpu.h | 2 +-
target-arm/translate-a64.c | 62 +++-------
target-arm/translate.c | 98 +++++-----------
target-arm/translate.h | 8 +-
target-cris/cpu.h | 1 -
target-cris/translate.c | 93 ++++-----------
target-cris/translate_v10.c | 3 -
target-i386/cpu.h | 2 +-
target-i386/translate.c | 106 +++++------------
target-lm32/cpu.h | 1 -
target-lm32/translate.c | 83 ++++----------
target-m68k/cpu.h | 1 -
target-m68k/translate.c | 82 ++++----------
target-microblaze/cpu.h | 1 -
target-microblaze/translate.c | 83 ++++----------
target-mips/cpu.h | 2 +-
target-mips/translate.c | 98 +++++-----------
target-moxie/cpu.h | 1 -
target-moxie/translate.c | 82 +++++---------
target-openrisc/cpu.h | 1 -
target-openrisc/translate.c | 78 +++----------
target-ppc/cpu.h | 1 -
target-ppc/translate.c | 72 ++++--------
target-s390x/cpu.h | 2 +-
target-s390x/translate.c | 78 ++++---------
target-sh4/cpu.h | 2 +-
target-sh4/translate.c | 91 +++++----------
target-sparc/cpu.h | 2 +-
target-sparc/translate.c | 185 +++++++++++++-----------------
target-tilegx/translate.c | 58 +++-------
target-tricore/translate.c | 59 ++++------
target-unicore32/translate.c | 83 ++++----------
target-xtensa/cpu.h | 1 -
target-xtensa/translate.c | 79 ++++---------
tcg/tcg-op.h | 52 +++++++--
tcg/tcg-opc.h | 4 +-
tcg/tcg.c | 127 +++++++++++----------
tcg/tcg.h | 16 ++-
tci.c | 9 --
translate-all.c | 258 ++++++++++++++++++++++++++----------------
44 files changed, 782 insertions(+), 1378 deletions(-)
--
2.1.0
- [Qemu-devel] [PATCH v2 00/22] Do away with TB retranslation,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 06/22] target-arm: Add condexec state to insn_start, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 05/22] tcg: Allow extra data to be attached to insn_start, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 03/22] target-*: Increment num_insns immediately after tcg_gen_insn_start, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 01/22] tcg: Rename debug_insn_start to insn_start, Richard Henderson, 2015/09/18
- [Qemu-devel] [PATCH v2 02/22] target-*: Unconditionally emit tcg_gen_insn_start, Richard Henderson, 2015/09/18