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[Qemu-devel] [PULL 25/35] target-tilegx: Handle bitfield instructions
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 25/35] target-tilegx: Handle bitfield instructions |
Date: |
Tue, 15 Sep 2015 08:04:03 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-tilegx/translate.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 168b4da..ba56a2e 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1125,13 +1125,87 @@ static TileExcp gen_bf_opcode_x0(DisasContext *dc,
unsigned ext,
unsigned dest, unsigned srca,
unsigned bfs, unsigned bfe)
{
+ TCGv tdest = dest_gr(dc, dest);
+ TCGv tsrca = load_gr(dc, srca);
+ TCGv tsrcd;
+ int len;
const char *mnemonic;
+ /* The bitfield is either between E and S inclusive,
+ or up from S and down from E inclusive. */
+ if (bfs <= bfe) {
+ len = bfe - bfs + 1;
+ } else {
+ len = (64 - bfs) + (bfe + 1);
+ }
+
switch (ext) {
case BFEXTU_BF_OPCODE_X0:
+ if (bfs == 0 && bfe == 7) {
+ tcg_gen_ext8u_tl(tdest, tsrca);
+ } else if (bfs == 0 && bfe == 15) {
+ tcg_gen_ext16u_tl(tdest, tsrca);
+ } else if (bfs == 0 && bfe == 31) {
+ tcg_gen_ext32u_tl(tdest, tsrca);
+ } else {
+ int rol = 63 - bfe;
+ if (bfs <= bfe) {
+ tcg_gen_shli_tl(tdest, tsrca, rol);
+ } else {
+ tcg_gen_rotli_tl(tdest, tsrca, rol);
+ }
+ tcg_gen_shri_tl(tdest, tdest, (bfs + rol) & 63);
+ }
+ mnemonic = "bfextu";
+ break;
+
case BFEXTS_BF_OPCODE_X0:
+ if (bfs == 0 && bfe == 7) {
+ tcg_gen_ext8s_tl(tdest, tsrca);
+ } else if (bfs == 0 && bfe == 15) {
+ tcg_gen_ext16s_tl(tdest, tsrca);
+ } else if (bfs == 0 && bfe == 31) {
+ tcg_gen_ext32s_tl(tdest, tsrca);
+ } else {
+ int rol = 63 - bfe;
+ if (bfs <= bfe) {
+ tcg_gen_shli_tl(tdest, tsrca, rol);
+ } else {
+ tcg_gen_rotli_tl(tdest, tsrca, rol);
+ }
+ tcg_gen_sari_tl(tdest, tdest, (bfs + rol) & 63);
+ }
+ mnemonic = "bfexts";
+ break;
+
case BFINS_BF_OPCODE_X0:
+ tsrcd = load_gr(dc, dest);
+ if (bfs <= bfe) {
+ tcg_gen_deposit_tl(tdest, tsrcd, tsrca, bfs, len);
+ } else {
+ tcg_gen_rotri_tl(tdest, tsrcd, bfs);
+ tcg_gen_deposit_tl(tdest, tdest, tsrca, 0, len);
+ tcg_gen_rotli_tl(tdest, tdest, bfs);
+ }
+ mnemonic = "bfins";
+ break;
+
case MM_BF_OPCODE_X0:
+ tsrcd = load_gr(dc, dest);
+ if (bfs == 0) {
+ tcg_gen_deposit_tl(tdest, tsrca, tsrcd, 0, len);
+ } else {
+ uint64_t mask = len == 64 ? -1 : rol64((1ULL << len) - 1, bfs);
+ TCGv tmp = tcg_const_tl(mask);
+
+ tcg_gen_and_tl(tdest, tsrcd, tmp);
+ tcg_gen_andc_tl(tmp, tsrca, tmp);
+ tcg_gen_or_tl(tdest, tdest, tmp);
+ tcg_temp_free(tmp);
+ }
+ mnemonic = "mm";
+ break;
+
default:
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
--
2.4.3
- [Qemu-devel] [PULL 16/35] host-utils: Add revbit functions, (continued)
- [Qemu-devel] [PULL 16/35] host-utils: Add revbit functions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 15/35] target-tilegx: Handle arithmetic instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 22/35] target-tilegx: Handle conditional branch instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 18/35] target-tilegx: Handle most bit manipulation instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 20/35] target-tilegx: Handle post-increment load and store instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 11/35] target-tilegx: Framework for decoding bundles, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 23/35] target-tilegx: Handle comparison instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 19/35] target-tilegx: Handle basic load and store instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 14/35] target-tilegx: Handle simple logical operations, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 27/35] target-tilegx: Handle conditional move instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 25/35] target-tilegx: Handle bitfield instructions,
Richard Henderson <=
- [Qemu-devel] [PULL 21/35] target-tilegx: Handle unconditional jump instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 24/35] target-tilegx: Implement system and memory management instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 30/35] target-tilegx: Handle v1cmpeq, v1cmpne, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 26/35] target-tilegx: Handle shift instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 33/35] target-tilegx: Handle v4int_l/h, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 28/35] target-tilegx: Handle scalar multiply instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 29/35] target-tilegx: Handle mask instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 31/35] target-tilegx: Handle mtspr, mfspr, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 32/35] target-tilegx: Handle atomic instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 34/35] target-tilegx: Handle v1shli, v1shrui, Richard Henderson, 2015/09/15