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[Qemu-devel] [PATCH v16 29/35] target-tilegx: Handle mask instructions
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v16 29/35] target-tilegx: Handle mask instructions |
Date: |
Mon, 14 Sep 2015 15:43:36 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-tilegx/translate.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 943b8a2..38f9389 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -643,11 +643,15 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
case OE_RRR(FSINGLE_MUL2, 0, X0):
case OE_RRR(FSINGLE_PACK2, 0, X0):
case OE_RRR(FSINGLE_SUB1, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(MNZ, 0, X0):
case OE_RRR(MNZ, 0, X1):
case OE_RRR(MNZ, 4, Y0):
case OE_RRR(MNZ, 4, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ t0 = load_zero(dc);
+ tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0);
+ mnemonic = "mnz";
+ break;
case OE_RRR(MULAX, 0, X0):
case OE_RRR(MULAX, 3, Y0):
tcg_gen_mul_tl(tdest, tsrca, tsrcb);
@@ -763,7 +767,10 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
case OE_RRR(MZ, 0, X1):
case OE_RRR(MZ, 4, Y0):
case OE_RRR(MZ, 4, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ t0 = load_zero(dc);
+ tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0);
+ mnemonic = "mz";
+ break;
case OE_RRR(NOR, 0, X0):
case OE_RRR(NOR, 0, X1):
case OE_RRR(NOR, 5, Y0):
--
2.4.3
- [Qemu-devel] [PATCH v16 19/35] target-tilegx: Handle basic load and store instructions, (continued)
- [Qemu-devel] [PATCH v16 19/35] target-tilegx: Handle basic load and store instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 20/35] target-tilegx: Handle post-increment load and store instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 22/35] target-tilegx: Handle conditional branch instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 23/35] target-tilegx: Handle comparison instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 21/35] target-tilegx: Handle unconditional jump instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 25/35] target-tilegx: Handle bitfield instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 24/35] target-tilegx: Implement system and memory management instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 26/35] target-tilegx: Handle shift instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 28/35] target-tilegx: Handle scalar multiply instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 27/35] target-tilegx: Handle conditional move instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 29/35] target-tilegx: Handle mask instructions,
Richard Henderson <=
- [Qemu-devel] [PATCH v16 30/35] target-tilegx: Handle v1cmpeq, v1cmpne, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 34/35] target-tilegx: Handle v1shli, v1shrui, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 31/35] target-tilegx: Handle mtspr, mfspr, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 32/35] target-tilegx: Handle atomic instructions, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 33/35] target-tilegx: Handle v4int_l/h, Richard Henderson, 2015/09/14
- [Qemu-devel] [PATCH v16 35/35] target-tilegx: Handle v1shl, v1shru, v1shrs, Richard Henderson, 2015/09/14
- Re: [Qemu-devel] [PATCH v16 00/35] TileGX basic instructions, Peter Maydell, 2015/09/15