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[Qemu-devel] [PULL 23/24] target-arm: Break out mpidr_read_val()
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 23/24] target-arm: Break out mpidr_read_val() |
Date: |
Mon, 14 Sep 2015 14:53:10 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Break out mpidr_read_val() to allow future sharing of the
code that conditionally sets the M and U bits of MPIDR.
No functional changes.
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d18106c..86900c2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2457,7 +2457,7 @@ static uint64_t midr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
return raw_read(env, ri);
}
-static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+static uint64_t mpidr_read_val(CPUARMState *env)
{
ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
uint64_t mpidr = cpu->mp_affinity;
@@ -2475,6 +2475,11 @@ static uint64_t mpidr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
return mpidr;
}
+static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ return mpidr_read_val(env);
+}
+
static const ARMCPRegInfo mpidr_cp_reginfo[] = {
{ .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
--
1.9.1
- [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 23/24] target-arm: Break out mpidr_read_val(),
Peter Maydell <=
- [Qemu-devel] [PULL 24/24] target-arm: Add VMPIDR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 20/24] target-arm: Suppress TBI for S2 translations, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 21/24] target-arm: Suppress EPD for S2, EL2 and EL3 translations, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 22/24] target-arm: Add VPIDR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 17/24] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 19/24] target-arm: Add VTTBR_EL2, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 13/24] target-arm: Use tcg_gen_extrh_i64_i32, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 08/24] target-arm: Implement fcsel with movcond, Peter Maydell, 2015/09/14
- [Qemu-devel] [PULL 07/24] target-arm: Implement ccmp branchless, Peter Maydell, 2015/09/14