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Re: [Qemu-devel] [PULL 00/20] target-arm queue
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL 00/20] target-arm queue |
Date: |
Tue, 8 Sep 2015 20:08:18 +0100 |
On 8 September 2015 at 17:51, Peter Maydell <address@hidden> wrote:
>
> Another week, another pullreq...
>
> -- PMM
>
> The following changes since commit 8611280505119e296757a60711a881341603fa5a:
>
> target-microblaze: Use setcond for pcmp* (2015-09-08 08:49:33 +0200)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20150908
>
> for you to fetch changes up to 6fdf3282d16e7fb6e798824fb5f4f60c6a73067d:
>
> xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP (2015-09-08 17:38:45 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Implement priority handling properly via GICC_APR
> * Enable TZ extensions on the GIC if we're using them
> * Minor preparatory patches for EL3 support
> * cadence_gem: Correct Marvell PHY SPCFC reset value
> * Support AHCI in ZynqMP
Applied, thanks.
-- PMM
- [Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using internal GIC state, (continued)
- [Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using internal GIC state, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 08/20] hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 04/20] hw/intc/arm_gic: Drop running_irq and last_active arrays, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 12/20] target-arm: Fix default_exception_el() function for the case when EL3 is not supported, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 07/20] hw/arm: new interface for devices which need to behave differently for kernel boot, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 17/20] ahci: Separate the AHCI state structure into the header, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 10/20] hw/arm/virt: Default to not providing TrustZone support, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 09/20] hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 02/20] hw/intc/arm_gic: Running priority is group priority, not full priority, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 03/20] hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers, Peter Maydell, 2015/09/08
- Re: [Qemu-devel] [PULL 00/20] target-arm queue,
Peter Maydell <=