[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 15/20] target-arm: Add AArch64 access to PAR_EL1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/20] target-arm: Add AArch64 access to PAR_EL1 |
Date: |
Tue, 8 Sep 2015 17:51:27 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 38a05e1..fc4b65f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2993,6 +2993,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
.access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
+ { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_ALIAS,
+ .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
+ .access = PL1_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
+ .writefn = par_write },
#endif
/* TLB invalidate last level of translation table walk */
{ .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
--
1.9.1
- [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 19/20] xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 20/20] xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 18/20] ahci.c: Don't assume AHCIState's parent is AHCIPCIState, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 16/20] cadence_gem: Correct Marvell PHY SPCFC reset value, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 15/20] target-arm: Add AArch64 access to PAR_EL1,
Peter Maydell <=
- [Qemu-devel] [PULL 14/20] target-arm: Correct opc1 for AT_S12Exx, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 13/20] target-arm: Log the target EL when taking exceptions, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 11/20] hw/arm/virt: Enable TZ extensions on the GIC if we are using them, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 06/20] qom: Add recursive version of object_child_for_each, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 05/20] hw/intc/arm_gic: Actually set the active bits for active interrupts, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using internal GIC state, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 08/20] hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 04/20] hw/intc/arm_gic: Drop running_irq and last_active arrays, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 12/20] target-arm: Fix default_exception_el() function for the case when EL3 is not supported, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 07/20] hw/arm: new interface for devices which need to behave differently for kernel boot, Peter Maydell, 2015/09/08