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Re: [Qemu-devel] [PATCH v1 07/10] target-arm: Supress the use of TTBR1 f


From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH v1 07/10] target-arm: Supress the use of TTBR1 for S2 translations
Date: Tue, 8 Sep 2015 15:50:34 +0100

On 8 September 2015 at 15:42, Edgar E. Iglesias
<address@hidden> wrote:
> On Tue, Sep 08, 2015 at 03:32:36PM +0100, Peter Maydell wrote:
>> On 3 September 2015 at 21:14, Edgar E. Iglesias
>> <address@hidden> wrote:
>> > From: "Edgar E. Iglesias" <address@hidden>
>> >
>> > Stage-2 MMU translations do not use TTBR1.
>> >
>> > Signed-off-by: Edgar E. Iglesias <address@hidden>
>> > ---
>> >  target-arm/helper.c | 5 +++++
>> >  1 file changed, 5 insertions(+)
>> >
>> > diff --git a/target-arm/helper.c b/target-arm/helper.c
>> > index 9ea9719..66b3fed 100644
>> > --- a/target-arm/helper.c
>> > +++ b/target-arm/helper.c
>> > @@ -6372,6 +6372,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, 
>> > target_ulong address,
>> >          }
>> >      }
>> >
>> > +    /* Stage2 translations do not use TTBR1.  */
>> > +    if (mmu_idx == ARMMMUIdx_S2NS) {
>> > +        ttbr1_valid = false;
>> > +    }
>> > +
>>
>> I think this is unnecessary, because we've already set ttbr1_valid
>> to false in the previous chunk of code for the case where el == 2
>> (as it is for stage 2 translations).
>
> I think we may be confused here.
>
> Note S2NS translations are controlled by EL2 but apply to NS EL0 and EL1.

Yep. el is the result of regime_el(), which returns what the ARM ARM
calls "the EL that the translation regime is controlled from".
In particular, we do things this way because it's the register width
of the controlling EL that determines whether the translation
regime is 64 bit, whether the TCR/TTBR/etc registers are the 64-bit
forms or not, etc.

thanks
-- PMM



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