Re: [Qemu-devel] [PATCH 3/4] target-arm: Implement missing AFSR registers

[Edgar E. Iglesias]

On Thu, Jul 30, 2015 at 07:36:37PM +0100, Peter Maydell wrote:
> The AFSR registers are implementation dependent auxiliary fault
> status registers. We already implemented a RAZ/WI AFSR0_EL1 and
> AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency.
> 
> Signed-off-by: Peter Maydell <address@hidden>

Reviewed-by: Edgar E. Iglesias <address@hidden>


> ---
>  target-arm/helper.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 781b3a2..d286680 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2610,6 +2610,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>        .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
>        .access = PL2_RW, .type = ARM_CP_CONST,
>        .resetvalue = 0 },
> +    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
> +    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> @@ -2713,6 +2721,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>        .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
>        .access = PL2_RW, .type = ARM_CP_CONST,
>        .resetvalue = 0 },
> +    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
> +    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
>        .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
> @@ -2819,6 +2835,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
>        .access = PL3_RW, .type = ARM_CP_CONST,
>        .resetvalue = 0 },
> +    { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
> +      .access = PL3_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
> +    { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
> +      .access = PL3_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      REGINFO_SENTINEL
>  };
>  
> -- 
> 1.9.1
>