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[Qemu-devel] [PULL 25/27] hw/arm/virt: Wire up secure timer interrupt
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 25/27] hw/arm/virt: Wire up secure timer interrupt |
Date: |
Thu, 13 Aug 2015 11:44:45 +0100 |
Wire up the secure timer interrupt. Since we've defined
that the plain old physical timer is the NS timer, we can
drop the now-out-of-date comment about QEMU not having TZ.
Use a data-driven loop to wire up the timer interrupts, since
we now have four of them and the code is the same for each.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
hw/arm/virt.c | 28 +++++++++++++++-------------
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 94694d6..d5a8417 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -391,20 +391,22 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic)
for (i = 0; i < smp_cpus; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
- /* physical timer; we wire it up to the non-secure timer's ID,
- * since a real A15 always has TrustZone but QEMU doesn't.
+ int irq;
+ /* Mapping from the output timer irq lines from the CPU to the
+ * GIC PPI inputs we use for the virt board.
*/
- qdev_connect_gpio_out(cpudev, 0,
- qdev_get_gpio_in(gicdev,
- ppibase + ARCH_TIMER_NS_EL1_IRQ));
- /* virtual timer */
- qdev_connect_gpio_out(cpudev, 1,
- qdev_get_gpio_in(gicdev,
- ppibase + ARCH_TIMER_VIRT_IRQ));
- /* Hypervisor timer. */
- qdev_connect_gpio_out(cpudev, 2,
- qdev_get_gpio_in(gicdev,
- ppibase + ARCH_TIMER_NS_EL2_IRQ));
+ const int timer_irq[] = {
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
+ [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
+ };
+
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
+ qdev_connect_gpio_out(cpudev, irq,
+ qdev_get_gpio_in(gicdev,
+ ppibase + timer_irq[irq]));
+ }
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev,
ARM_CPU_IRQ));
sysbus_connect_irq(gicbusdev, i + smp_cpus,
--
1.9.1
- [Qemu-devel] [PULL 02/27] target-arm: Add CNTHCTL_EL2, (continued)
- [Qemu-devel] [PULL 02/27] target-arm: Add CNTHCTL_EL2, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 14/27] i.MX: Fix Coding style for CCM emulator, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 27/27] i.MX: Fix UART driver to work with unitialized "chardev" device, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 07/27] hw/arm/virt: Connect the Hypervisor timer, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 11/27] i.MX: Split AVIC emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 03/27] target-arm: Rename and move gt_cnt_reset, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 13/27] i.MX: Split CCM emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 08/27] i.MX: Split UART emulator in a header file and a source file, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 05/27] target-arm: Add the Hypervisor timer, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 21/27] Introduce gic_class_name() instead of repeating condition, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 25/27] hw/arm/virt: Wire up secure timer interrupt,
Peter Maydell <=
- [Qemu-devel] [PULL 09/27] i.MX: Move serial initialization to init/realize of DeviceClass., Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 26/27] hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts, Peter Maydell, 2015/08/13
- [Qemu-devel] [PULL 04/27] target-arm: Pass timeridx as argument to various timer functions, Peter Maydell, 2015/08/13
- Re: [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2015/08/13