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Re: [Qemu-devel] [Qemu-ppc] [PATCH v2] pci: allow 0 address for PCI IO/M

From: Peter Maydell
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH v2] pci: allow 0 address for PCI IO/MEM regions
Date: Thu, 23 Jul 2015 22:00:30 +0100

On 23 July 2015 at 21:46, Benjamin Herrenschmidt
<address@hidden> wrote:
> On Thu, 2015-07-23 at 20:24 +0200, Laurent Vivier wrote:
>> From: Michael Roth <address@hidden>
>> Some kernels program a 0 address for io regions. PCI 3.0 spec
>> section doesn't seem to disallow this.
>> Signed-off-by: Michael Roth <address@hidden>
>> [lvivier: add pci_allow_0_addr in MachineClass to conditionally
>> allow addr 0 for pseries, as this can break other architectures]
>> Signed-off-by: Laurent Vivier <address@hidden>
>> ---
> Why would it break other architectures ? The PCI bus will forward
> address 0 just fine and some devices will decode it just fine too,
> regardless of the architecture they are put on. I don't see why
> having BARs capable of decoding it would break anything...

Discussion from last time around:

suggests that it's a workaround for our PC model being buggy
and putting 0-address BARs over the top of some other system
device rather than underneath them...

(Also, none of our PCI device models actually try to do
the "BAR at zero means I won't respond" behaviour, which
presumably they might do in real life.)

-- PMM

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