Re: [Qemu-devel] [PATCH v2 4/6] hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs

[Peter Crosthwaite]

On Thu, Jul 16, 2015 at 1:11 PM, Peter Maydell <address@hidden> wrote:
> If the A9 and A15 CPUs which we're creating the peripherals for have
> TrustZone (EL3) enabled, then also enable it in the GIC we create.
>
> Signed-off-by: Peter Maydell <address@hidden>

Reviewed-by: Peter Crosthwaite <address@hidden>

---
P.S. My mail setup will be fixed shortly and ill be replying from the
same address as giving the RBs.

Regards,
Peter

> ---
>  hw/cpu/a15mpcore.c | 13 +++++++++++++
>  hw/cpu/a9mpcore.c  | 11 +++++++++++
>  2 files changed, 24 insertions(+)
>
> diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
> index 49727d0..fd0c46a 100644
> --- a/hw/cpu/a15mpcore.c
> +++ b/hw/cpu/a15mpcore.c
> @@ -56,10 +56,23 @@ static void a15mp_priv_realize(DeviceState *dev, Error 
> **errp)
>      SysBusDevice *busdev;
>      int i;
>      Error *err = NULL;
> +    bool has_el3;
> +    Object *cpuobj;
>
>      gicdev = DEVICE(&s->gic);
>      qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
>      qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
> +
> +    if (!kvm_irqchip_in_kernel()) {
> +        /* Make the GIC's TZ support match the CPUs. We assume that
> +         * either all the CPUs have TZ, or none do.
> +         */
> +        cpuobj = OBJECT(qemu_get_cpu(0));
> +        has_el3 = object_property_find(cpuobj, "has_el3", &error_abort) &&
> +            object_property_get_bool(cpuobj, "has_el3", &error_abort);
> +        qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
> +    }
> +
>      object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
>      if (err != NULL) {
>          error_propagate(errp, err);
> diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
> index c09358c..7046246 100644
> --- a/hw/cpu/a9mpcore.c
> +++ b/hw/cpu/a9mpcore.c
> @@ -49,6 +49,8 @@ static void a9mp_priv_realize(DeviceState *dev, Error 
> **errp)
>                   *wdtbusdev;
>      Error *err = NULL;
>      int i;
> +    bool has_el3;
> +    Object *cpuobj;
>
>      scudev = DEVICE(&s->scu);
>      qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
> @@ -62,6 +64,15 @@ static void a9mp_priv_realize(DeviceState *dev, Error 
> **errp)
>      gicdev = DEVICE(&s->gic);
>      qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
>      qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
> +
> +    /* Make the GIC's TZ support match the CPUs. We assume that
> +     * either all the CPUs have TZ, or none do.
> +     */
> +    cpuobj = OBJECT(qemu_get_cpu(0));
> +    has_el3 = object_property_find(cpuobj, "has_el3", &error_abort) &&
> +        object_property_get_bool(cpuobj, "has_el3", &error_abort);
> +    qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
> +
>      object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
>      if (err != NULL) {
>          error_propagate(errp, err);
> --
> 1.9.1
>
>