Re: [Qemu-devel] [PATCH v2 3/9] target-microblaze: Convert dcache-writeback to a CPU property

[Peter Crosthwaite]

On Mon, Jun 8, 2015 at 4:31 PM, Peter Crosthwaite
<address@hidden> wrote:
> From: Alistair Francis <address@hidden>
>
> Originally  the dcache-writeback PVR bits were manually set for each machine.
> This is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis <address@hidden>
> Reviewed-by: Edgar E. Iglesias <address@hidden>

Reviewed-by: Peter Crosthwaite <address@hidden>

> ---
>  hw/microblaze/petalogix_ml605_mmu.c |    3 ++-
>  target-microblaze/cpu-qom.h         |    1 +
>  target-microblaze/cpu.c             |    5 +++++
>  3 files changed, 8 insertions(+), 1 deletions(-)
>
> diff --git a/hw/microblaze/petalogix_ml605_mmu.c 
> b/hw/microblaze/petalogix_ml605_mmu.c
> index 05c120a..995a579 100644
> --- a/hw/microblaze/petalogix_ml605_mmu.c
> +++ b/hw/microblaze/petalogix_ml605_mmu.c
> @@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
>
>      env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
>      /* setup pvr to match kernel setting */
> -    env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK;
>      env->pvr.regs[0] |= PVR0_ENDI;
>      env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
>      env->pvr.regs[4] = 0xc56b8000;
> @@ -98,6 +97,8 @@ petalogix_ml605_init(MachineState *machine)
>       * root instructions
>       */
>      object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
> +    object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
> +                             &error_abort);
>      object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
>
>      /* Attach emulated BRAM through the LMB.  */
> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
> index 6bde2e9..3b6165d 100644
> --- a/target-microblaze/cpu-qom.h
> +++ b/target-microblaze/cpu-qom.h
> @@ -65,6 +65,7 @@ typedef struct MicroBlazeCPU {
>          uint32_t base_vectors;
>          uint8_t use_fpu;
>          bool use_mmu;
> +        bool dcache_writeback;
>      } cfg;
>
>      CPUMBState env;
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index c4cd68a..92c51a0 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -119,6 +119,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error 
> **errp)
>      env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
>                          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
>
> +    env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
> +                                        PVR5_DCACHE_WRITEBACK_MASK : 0;
> +
>      env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
>      env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
>
> @@ -169,6 +172,8 @@ static Property mb_properties[] = {
>       */
>      DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
>      DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
> +    DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
> +                     false),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> --
> 1.7.1
>