Re: [Qemu-devel] [PATCH 1/5] hw/arm/pxa2xx: Mark coprocessor registers as ARM_CP_IO

[Peter Crosthwaite]

On Thu, May 28, 2015 at 5:09 AM, Peter Maydell <address@hidden> wrote:
> The pxa2xx custom coprocessor registers in cp6 and cp14 do device
> accesses, so mark the non-constant regs as ARM_CP_IO so that
> icount works correctly and doesn't abort.
>
> Signed-off-by: Peter Maydell <address@hidden>

Reviewed-by: Peter Crosthwaite <address@hidden>

I'm guessing some of the more trivial callback fn's don't actually
need this but I think setting the IO flag across the board is probably
the correct policy.

Regards,
Peter

> ---
>  hw/arm/pxa2xx.c     | 8 ++++----
>  hw/arm/pxa2xx_pic.c | 2 +-
>  2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
> index f921a56..8123f05 100644
> --- a/hw/arm/pxa2xx.c
> +++ b/hw/arm/pxa2xx.c
> @@ -334,10 +334,10 @@ static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, 
> const ARMCPRegInfo *ri)
>  static const ARMCPRegInfo pxa_cp_reginfo[] = {
>      /* cp14 crm==1: perf registers */
>      { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
> -      .access = PL1_RW,
> +      .access = PL1_RW, .type = ARM_CP_IO,
>        .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
>      { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> -      .access = PL1_RW,
> +      .access = PL1_RW, .type = ARM_CP_IO,
>        .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
>      { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
>        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> @@ -356,11 +356,11 @@ static const ARMCPRegInfo pxa_cp_reginfo[] = {
>        .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
>      /* cp14 crn==6: CLKCFG */
>      { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
> -      .access = PL1_RW,
> +      .access = PL1_RW, .type = ARM_CP_IO,
>        .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
>      /* cp14 crn==7: PWRMODE */
>      { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
> -      .access = PL1_RW,
> +      .access = PL1_RW, .type = ARM_CP_IO,
>        .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
>      REGINFO_SENTINEL
>  };
> diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
> index 9cfc714..d41ac93 100644
> --- a/hw/arm/pxa2xx_pic.c
> +++ b/hw/arm/pxa2xx_pic.c
> @@ -232,7 +232,7 @@ static void pxa2xx_pic_cp_write(CPUARMState *env, const 
> ARMCPRegInfo *ri,
>
>  #define REGINFO_FOR_PIC_CP(NAME, CRN) \
>      { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
> -      .access = PL1_RW, \
> +      .access = PL1_RW, .type = ARM_CP_IO, \
>        .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
>
>  static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
> --
> 1.9.1
>
>