Re: [Qemu-devel] [PATCH 03/14] target-arm: Set correct syndrome for faults on MSR DAIF*, imm

[Peter Maydell]

On 28 May 2015 at 09:30, Peter Maydell <address@hidden> wrote:
> On 28 May 2015 at 06:30, Edgar E. Iglesias <address@hidden> wrote:
>>> @@ -381,6 +381,9 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t 
>>> op, uint32_t imm)
>>>       */
>>>      if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
>>>          env->exception.target_el = exception_target_el(env);
>>> +        env->exception.syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 
>>> 3),
>>> +                                                      extract32(op, 3, 3), 
>>> 4,
>>> +                                                      0x1f, imm, 0);
>>
>> Did you possibly reverse the argument order of 0x1f and imm?
>
> Ah, you're right; I was confused because the argument order of our
> syn_aa64_sysregtrap() and the pseudocode AArch64.SystemRegisterTrap
> is different (the latter follows the field order in the syndrome
> register and ours doesn't).

I also managed to forget the signoff:
Signed-off-by: Peter Maydell <address@hidden>

If this is the only fix in this series (I think you have one or two
patches still left to review) then I propose to add it as I put
the patches in target-arm.next:

-                                                      0x1f, imm, 0);
+                                                      imm, 0x1f, 0);

thanks
-- PMM